key_scan1.tan.qmsg

用verilog实现的四乘四键盘程序,在Quartus II上编译通过并成功

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk_in register div_clk:inst3\|k\[1\] register div_clk:inst3\|k\[31\] 74.63 MHz 13.4 ns Internal " "Info: Clock \"clk_in\" has Internal fmax of 74.63 MHz between source register \"div_clk:inst3\|k\[1\]\" and destination register \"div_clk:inst3\|k\[31\]\" (period= 13.4 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "12.300 ns + Longest register register " "Info: + Longest register to register delay is 12.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns div_clk:inst3\|k\[1\] 1 REG LC1_F30 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1_F30; Fanout = 3; REG Node = 'div_clk:inst3\|k\[1\]'" {  } { { "F:/verilog/jingshai/key_scan1/db/key_scan1_cmp.qrpt" "" { Report "F:/verilog/jingshai/key_scan1/db/key_scan1_cmp.qrpt" Compiler "key_scan1" "UNKNOWN" "V1" "F:/verilog/jingshai/key_scan1/db/key_scan1.quartus_db" { Floorplan "F:/verilog/jingshai/key_scan1/" "" "" { div_clk:inst3|k[1] } "NODE_NAME" } "" } } { "div_clk.v" "" { Text "F:/verilog/jingshai/key_scan1/div_clk.v" 11 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.100 ns) + CELL(0.700 ns) 1.800 ns div_clk:inst3\|lpm_add_sub:add_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[1\] 2 COMB LC2_F29 2 " "Info: 2: + IC(1.100 ns) + CELL(0.700 ns) = 1.800 ns; Loc. = LC2_F29; Fanout = 2; COMB Node = 'div_clk:inst3\|lpm_add_sub:add_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[1\]'" {  } { { "F:/verilog/jingshai/key_scan1/db/key_scan1_cmp.qrpt" "" { Report "F:/verilog/jingshai/key_scan1/db/key_scan1_cmp.qrpt" Compiler "key_scan1" "UNKNOWN" "V1" "F:/verilog/jingshai/key_scan1/db/key_scan1.quartus_db" { Floorplan "F:/verilog/jingshai/key_scan1/" "" "1.800 ns" { div_clk:inst3|k[1] div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[1] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quar5.0/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 2.000 ns div_clk:inst3\|lpm_add_sub:add_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[2\] 3 COMB LC3_F29 2 " "Info: 3: + IC(0.000 ns) + CELL(0.200 ns) = 2.000 ns; Loc. = LC3_F29; Fanout = 2; COMB Node = 'div_clk:inst3\|lpm_add_sub:add_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[2\]'" {  } { { "F:/verilog/jingshai/key_scan1/db/key_scan1_cmp.qrpt" "" { Report "F:/verilog/jingshai/key_scan1/db/key_scan1_cmp.qrpt" Compiler "key_scan1" "UNKNOWN" "V1" "F:/verilog/jingshai/key_scan1/db/key_scan1.quartus_db" { Floorplan "F:/verilog/jingshai/key_scan1/" "" "0.200 ns" { div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[1] div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[2] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quar5.0/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 2.200 ns div_clk:inst3\|lpm_add_sub:add_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[3\] 4 COMB LC4_F29 2 " "Info: 4: + IC(0.000 ns) + CELL(0.200 ns) = 2.200 ns; Loc. = LC4_F29; Fanout = 2; COMB Node = 'div_clk:inst3\|lpm_add_sub:add_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[3\]'" {  } { { "F:/verilog/jingshai/key_scan1/db/key_scan1_cmp.qrpt" "" { Report "F:/verilog/jingshai/key_scan1/db/key_scan1_cmp.qrpt" Compiler "key_scan1" "UNKNOWN" "V1" "F:/verilog/jingshai/key_scan1/db/key_scan1.quartus_db" { Floorplan "F:/verilog/jingshai/key_scan1/" "" "0.200 ns" { div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[2] div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[3] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quar5.0/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 2.400 ns div_clk:inst3\|lpm_add_sub:add_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[4\] 5 COMB LC5_F29 2 " "Info: 5: + IC(0.000 ns) + CELL(0.200 ns) = 2.400 ns; Loc. = LC5_F29; Fanout = 2; COMB Node = 'div_clk:inst3\|lpm_add_sub:add_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[4\]'" {  } { { "F:/verilog/jingshai/key_scan1/db/key_scan1_cmp.qrpt" "" { Report "F:/verilog/jingshai/key_scan1/db/key_scan1_cmp.qrpt" Compiler "key_scan1" "UNKNOWN" "V1" "F:/verilog/jingshai/key_scan1/db/key_scan1.quartus_db" { Floorplan "F:/verilog/jingshai/key_scan1/" "" "0.200 ns" { div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[3] div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[4] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quar5.0/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 2.600 ns div_clk:inst3\|lpm_add_sub:add_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[5\] 6 COMB LC6_F29 2 " "Info: 6: + IC(0.000 ns) + CELL(0.200 ns) = 2.600 ns; Loc. = LC6_F29; Fanout = 2; COMB Node = 'div_clk:inst3\|lpm_add_sub:add_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[5\]'" {  } { { "F:/verilog/jingshai/key_scan1/db/key_scan1_cmp.qrpt" "" { Report "F:/verilog/jingshai/key_scan1/db/key_scan1_cmp.qrpt" Compiler "key_scan1" "UNKNOWN" "V1" "F:/verilog/jingshai/key_scan1/db/key_scan1.quartus_db" { Floorplan "F:/verilog/jingshai/key_scan1/" "" "0.200 ns" { div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[4] div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[5] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quar5.0/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 2.800 ns div_clk:inst3\|lpm_add_sub:add_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[6\] 7 COMB LC7_F29 2 " "Info: 7: + IC(0.000 ns) + CELL(0.200 ns) = 2.800 ns; Loc. = LC7_F29; Fanout = 2; COMB Node = 'div_clk:inst3\|lpm_add_sub:add_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[6\]'" {  } { { "F:/verilog/jingshai/key_scan1/db/key_scan1_cmp.qrpt" "" { Report "F:/verilog/jingshai/key_scan1/db/key_scan1_cmp.qrpt" Compiler "key_scan1" "UNKNOWN" "V1" "F:/verilog/jingshai/key_scan1/db/key_scan1.quartus_db" { Floorplan "F:/verilog/jingshai/key_scan1/" "" "0.200 ns" { div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[5] div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[6] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quar5.0/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 3.000 ns div_clk:inst3\|lpm_add_sub:add_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[7\] 8 COMB LC8_F29 2 " "Info: 8: + IC(0.000 ns) + CELL(0.200 ns) = 3.000 ns; Loc. = LC8_F29; Fanout = 2; COMB Node = 'div_clk:inst3\|lpm_add_sub:add_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[7\]'" {  } { { "F:/verilog/jingshai/key_scan1/db/key_scan1_cmp.qrpt" "" { Report "F:/verilog/jingshai/key_scan1/db/key_scan1_cmp.qrpt" Compiler "key_scan1" "UNKNOWN" "V1" "F:/verilog/jingshai/key_scan1/db/key_scan1.quartus_db" { Floorplan "F:/verilog/jingshai/key_scan1/" "" "0.200 ns" { div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[6] div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[7] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quar5.0/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.500 ns) + CELL(0.200 ns) 3.700 ns div_clk:inst3\|lpm_add_sub:add_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[8\] 9 COMB LC1_F31 2 " "Info: 9: + IC(0.500 ns) + CELL(0.200 ns) = 3.700 ns; Loc. = LC1_F31; Fanout = 2; COMB Node = 'div_clk:inst3\|lpm_add_sub:add_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[8\]'" {  } { { "F:/verilog/jingshai/key_scan1/db/key_scan1_cmp.qrpt" "" { Report "F:/verilog/jingshai/key_scan1/db/key_scan1_cmp.qrpt" Compiler "key_scan1" "UNKNOWN" "V1" "F:/verilog/jingshai/key_scan1/db/key_scan1.quartus_db" { Floorplan "F:/verilog/jingshai/key_scan1/" "" "0.700 ns" { div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[7] div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[8] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quar5.0/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 3.900 ns div_clk:inst3\|lpm_add_sub:add_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[9\] 10 COMB LC2_F31 2 " "Info: 10: + IC(0.000 ns) + CELL(0.200 ns) = 3.900 ns; Loc. = LC2_F31; Fanout = 2; COMB Node = 'div_clk:inst3\|lpm_add_sub:add_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[9\]'" {  } { { "F:/verilog/jingshai/key_scan1/db/key_scan1_cmp.qrpt" "" { Report "F:/verilog/jingshai/key_scan1/db/key_scan1_cmp.qrpt" Compiler "key_scan1" "UNKNOWN" "V1" "F:/verilog/jingshai/key_scan1/db/key_scan1.quartus_db" { Floorplan "F:/verilog/jingshai/key_scan1/" "" "0.200 ns" { div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[8] div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[9] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quar5.0/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 4.100 ns div_clk:inst3\|lpm_add_sub:add_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[10\] 11 COMB LC3_F31 2 " "Info: 11: + IC(0.000 ns) + CELL(0.200 ns) = 4.100 ns; Loc. = LC3_F31; Fanout = 2; COMB Node = 'div_clk:inst3\|lpm_add_sub:add_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[10\]'" {  } { { "F:/verilog/jingshai/key_scan1/db/key_scan1_cmp.qrpt" "" { Report "F:/verilog/jingshai/key_scan1/db/key_scan1_cmp.qrpt" Compiler "key_scan1" "UNKNOWN" "V1" "F:/verilog/jingshai/key_scan1/db/key_scan1.quartus_db" { Floorplan "F:/verilog/jingshai/key_scan1/" "" "0.200 ns" { div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[9] div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[10] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quar5.0/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 4.300 ns div_clk:inst3\|lpm_add_sub:add_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[11\] 12 COMB LC4_F31 2 " "Info: 12: + IC(0.000 ns) + CELL(0.200 ns) = 4.300 ns; Loc. = LC4_F31; Fanout = 2; COMB Node = 'div_clk:inst3\|lpm_add_sub:add_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[11\]'" {  } { { "F:/verilog/jingshai/key_scan1/db/key_scan1_cmp.qrpt" "" { Report "F:/verilog/jingshai/key_scan1/db/key_scan1_cmp.qrpt" Compiler "key_scan1" "UNKNOWN" "V1" "F:/verilog/jingshai/key_scan1/db/key_scan1.quartus_db" { Floorplan "F:/verilog/jingshai/key_scan1/" "" "0.200 ns" { div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[10] div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[11] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quar5.0/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 4.500 ns div_clk:inst3\|lpm_add_sub:add_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[12\] 13 COMB LC5_F31 2 " "Info: 13: + IC(0.000 ns) + CELL(0.200 ns) = 4.500 ns; Loc. = LC5_F31; Fanout = 2; COMB Node = 'div_clk:inst3\|lpm_add_sub:add_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[12\]'" {  } { { "F:/verilog/jingshai/key_scan1/db/key_scan1_cmp.qrpt" "" { Report "F:/verilog/jingshai/key_scan1/db/key_scan1_cmp.qrpt" Compiler "key_scan1" "UNKNOWN" "V1" "F:/verilog/jingshai/key_scan1/db/key_scan1.quartus_db" { Floorplan "F:/verilog/jingshai/key_scan1/" "" "0.200 ns" { div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[11] div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[12] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quar5.0/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 4.700 ns div_clk:inst3\|lpm_add_sub:add_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[13\] 14 COMB LC6_F31 2 " "Info: 14: + IC(0.000 ns) + CELL(0.200 ns) = 4.700 ns; Loc. = LC6_F31; Fanout = 2; COMB Node = 'div_clk:inst3\|lpm_add_sub:add_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[13\]'" {  } { { "F:/verilog/jingshai/key_scan1/db/key_scan1_cmp.qrpt" "" { Report "F:/verilog/jingshai/key_scan1/db/key_scan1_cmp.qrpt" Compiler "key_scan1" "UNKNOWN" "V1" "F:/verilog/jingshai/key_scan1/db/key_scan1.quartus_db" { Floorplan "F:/verilog/jingshai/key_scan1/" "" "0.200 ns" { div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[12] div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[13] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quar5.0/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 4.900 ns div_clk:inst3\|lpm_add_sub:add_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[14\] 15 COMB LC7_F31 2 " "Info: 15: + IC(0.000 ns) + CELL(0.200 ns) = 4.900 ns; Loc. = LC7_F31; Fanout = 2; COMB Node = 'div_clk:inst3\|lpm_add_sub:add_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[14\]'" {  } { { "F:/verilog/jingshai/key_scan1/db/key_scan1_cmp.qrpt" "" { Report "F:/verilog/jingshai/key_scan1/db/key_scan1_cmp.qrpt" Compiler "key_scan1" "UNKNOWN" "V1" "F:/verilog/jingshai/key_scan1/db/key_scan1.quartus_db" { Floorplan "F:/verilog/jingshai/key_scan1/" "" "0.200 ns" { div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[13] div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[14] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quar5.0/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 5.100 ns div_clk:inst3\|lpm_add_sub:add_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[15\] 16 COMB LC8_F31 2 " "Info: 16: + IC(0.000 ns) + CELL(0.200 ns) = 5.100 ns; Loc. = LC8_F31; Fanout = 2; COMB Node = 'div_clk:inst3\|lpm_add_sub:add_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[15\]'" {  } { { "F:/verilog/jingshai/key_scan1/db/key_scan1_cmp.qrpt" "" { Report "F:/verilog/jingshai/key_scan1/db/key_scan1_cmp.qrpt" Compiler "key_scan1" "UNKNOWN" "V1" "F:/verilog/jingshai/key_scan1/db/key_scan1.quartus_db" { Floorplan "F:/verilog/jingshai/key_scan1/" "" "0.200 ns" { div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[14] div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[15] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quar5.0/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.500 ns) + CELL(0.200 ns) 5.800 ns div_clk:inst3\|lpm_add_sub:add_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[16\] 17 COMB LC1_F33 2 " "Info: 17: + IC(0.500 ns) + CELL(0.200 ns) = 5.800 ns; Loc. = LC1_F33; Fanout = 2; COMB Node = 'div_clk:inst3\|lpm_add_sub:add_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[16\]'" {  } { { "F:/verilog/jingshai/key_scan1/db/key_scan1_cmp.qrpt" "" { Report "F:/verilog/jingshai/key_scan1/db/key_scan1_cmp.qrpt" Compiler "key_scan1" "UNKNOWN" "V1" "F:/verilog/jingshai/key_scan1/db/key_scan1.quartus_db" { Floorplan "F:/verilog/jingshai/key_scan1/" "" "0.700 ns" { div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[15] div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[16] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quar5.0/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 6.000 ns div_clk:inst3\|lpm_add_sub:add_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[17\] 18 COMB LC2_F33 2 " "Info: 18: + IC(0.000 ns) + CELL(0.200 ns) = 6.000 ns; Loc. = LC2_F33; Fanout = 2; COMB Node = 'div_clk:inst3\|lpm_add_sub:add_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[17\]'" {  } { { "F:/verilog/jingshai/key_scan1/db/key_scan1_cmp.qrpt" "" { Report "F:/verilog/jingshai/key_scan1/db/key_scan1_cmp.qrpt" Compiler "key_scan1" "UNKNOWN" "V1" "F:/verilog/jingshai/key_scan1/db/key_scan1.quartus_db" { Floorplan "F:/verilog/jingshai/key_scan1/" "" "0.200 ns" { div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[16] div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[17] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quar5.0/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 6.200 ns div_clk:inst3\|lpm_add_sub:add_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[18\] 19 COMB LC3_F33 2 " "Info: 19: + IC(0.000 ns) + CELL(0.200 ns) = 6.200 ns; Loc. = LC3_F33; Fanout = 2; COMB Node = 'div_clk:inst3\|lpm_add_sub:add_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[18\]'" {  } { { "F:/verilog/jingshai/key_scan1/db/key_scan1_cmp.qrpt" "" { Report "F:/verilog/jingshai/key_scan1/db/key_scan1_cmp.qrpt" Compiler "key_scan1" "UNKNOWN" "V1" "F:/verilog/jingshai/key_scan1/db/key_scan1.quartus_db" { Floorplan "F:/verilog/jingshai/key_scan1/" "" "0.200 ns" { div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[17] div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[18] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quar5.0/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 6.400 ns div_clk:inst3\|lpm_add_sub:add_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[19\] 20 COMB LC4_F33 2 " "Info: 20: + IC(0.000 ns) + CELL(0.200 ns) = 6.400 ns; Loc. = LC4_F33; Fanout = 2; COMB Node = 'div_clk:inst3\|lpm_add_sub:add_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[19\]'" {  } { { "F:/verilog/jingshai/key_scan1/db/key_scan1_cmp.qrpt" "" { Report "F:/verilog/jingshai/key_scan1/db/key_scan1_cmp.qrpt" Compiler "key_scan1" "UNKNOWN" "V1" "F:/verilog/jingshai/key_scan1/db/key_scan1.quartus_db" { Floorplan "F:/verilog/jingshai/key_scan1/" "" "0.200 ns" { div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[18] div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[19] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quar5.0/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 6.600 ns div_clk:inst3\|lpm_add_sub:add_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[20\] 21 COMB LC5_F33 2 " "Info: 21: + IC(0.000 ns) + CELL(0.200 ns) = 6.600 ns; Loc. = LC5_F33; Fanout = 2; COMB Node = 'div_clk:inst3\|lpm_add_sub:add_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[20\]'" {  } { { "F:/verilog/jingshai/key_scan1/db/key_scan1_cmp.qrpt" "" { Report "F:/verilog/jingshai/key_scan1/db/key_scan1_cmp.qrpt" Compiler "key_scan1" "UNKNOWN" "V1" "F:/verilog/jingshai/key_scan1/db/key_scan1.quartus_db" { Floorplan "F:/verilog/jingshai/key_scan1/" "" "0.200 ns" { div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[19] div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[20] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quar5.0/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 6.800 ns div_clk:inst3\|lpm_add_sub:add_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[21\] 22 COMB LC6_F33 2 " "Info: 22: + IC(0.000 ns) + CELL(0.200 ns) = 6.800 ns; Loc. = LC6_F33; Fanout = 2; COMB Node = 'div_clk:inst3\|lpm_add_sub:add_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[21\]'" {  } { { "F:/verilog/jingshai/key_scan1/db/key_scan1_cmp.qrpt" "" { Report "F:/verilog/jingshai/key_scan1/db/key_scan1_cmp.qrpt" Compiler "key_scan1" "UNKNOWN" "V1" "F:/verilog/jingshai/key_scan1/db/key_scan1.quartus_db" { Floorplan "F:/verilog/jingshai/key_scan1/" "" "0.200 ns" { div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[20] div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[21] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quar5.0/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 7.000 ns div_clk:inst3\|lpm_add_sub:add_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[22\] 23 COMB LC7_F33 2 " "Info: 23: + IC(0.000 ns) + CELL(0.200 ns) = 7.000 ns; Loc. = LC7_F33; Fanout = 2; COMB Node = 'div_clk:inst3\|lpm_add_sub:add_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[22\]'" {  } { { "F:/verilog/jingshai/key_scan1/db/key_scan1_cmp.qrpt" "" { Report "F:/verilog/jingshai/key_scan1/db/key_scan1_cmp.qrpt" Compiler "key_scan1" "UNKNOWN" "V1" "F:/verilog/jingshai/key_scan1/db/key_scan1.quartus_db" { Floorplan "F:/verilog/jingshai/key_scan1/" "" "0.200 ns" { div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[21] div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[22] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quar5.0/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 7.200 ns div_clk:inst3\|lpm_add_sub:add_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[23\] 24 COMB LC8_F33 2 " "Info: 24: + IC(0.000 ns) + CELL(0.200 ns) = 7.200 ns; Loc. = LC8_F33; Fanout = 2; COMB Node = 'div_clk:inst3\|lpm_add_sub:add_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[23\]'" {  } { { "F:/verilog/jingshai/key_scan1/db/key_scan1_cmp.qrpt" "" { Report "F:/verilog/jingshai/key_scan1/db/key_scan1_cmp.qrpt" Compiler "key_scan1" "UNKNOWN" "V1" "F:/verilog/jingshai/key_scan1/db/key_scan1.quartus_db" { Floorplan "F:/verilog/jingshai/key_scan1/" "" "0.200 ns" { div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[22] div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[23] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quar5.0/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.500 ns) + CELL(0.200 ns) 7.900 ns div_clk:inst3\|lpm_add_sub:add_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[24\] 25 COMB LC1_F35 2 " "Info: 25: + IC(0.500 ns) + CELL(0.200 ns) = 7.900 ns; Loc. = LC1_F35; Fanout = 2; COMB Node = 'div_clk:inst3\|lpm_add_sub:add_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[24\]'" {  } { { "F:/verilog/jingshai/key_scan1/db/key_scan1_cmp.qrpt" "" { Report "F:/verilog/jingshai/key_scan1/db/key_scan1_cmp.qrpt" Compiler "key_scan1" "UNKNOWN" "V1" "F:/verilog/jingshai/key_scan1/db/key_scan1.quartus_db" { Floorplan "F:/verilog/jingshai/key_scan1/" "" "0.700 ns" { div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[23] div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[24] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quar5.0/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 8.100 ns div_clk:inst3\|lpm_add_sub:add_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[25\] 26 COMB LC2_F35 2 " "Info: 26: + IC(0.000 ns) + CELL(0.200 ns) = 8.100 ns; Loc. = LC2_F35; Fanout = 2; COMB Node = 'div_clk:inst3\|lpm_add_sub:add_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[25\]'" {  } { { "F:/verilog/jingshai/key_scan1/db/key_scan1_cmp.qrpt" "" { Report "F:/verilog/jingshai/key_scan1/db/key_scan1_cmp.qrpt" Compiler "key_scan1" "UNKNOWN" "V1" "F:/verilog/jingshai/key_scan1/db/key_scan1.quartus_db" { Floorplan "F:/verilog/jingshai/key_scan1/" "" "0.200 ns" { div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[24] div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[25] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quar5.0/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 8.300 ns div_clk:inst3\|lpm_add_sub:add_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[26\] 27 COMB LC3_F35 2 " "Info: 27: + IC(0.000 ns) + CELL(0.200 ns) = 8.300 ns; Loc. = LC3_F35; Fanout = 2; COMB Node = 'div_clk:inst3\|lpm_add_sub:add_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[26\]'" {  } { { "F:/verilog/jingshai/key_scan1/db/key_scan1_cmp.qrpt" "" { Report "F:/verilog/jingshai/key_scan1/db/key_scan1_cmp.qrpt" Compiler "key_scan1" "UNKNOWN" "V1" "F:/verilog/jingshai/key_scan1/db/key_scan1.quartus_db" { Floorplan "F:/verilog/jingshai/key_scan1/" "" "0.200 ns" { div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[25] div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[26] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quar5.0/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 8.500 ns div_clk:inst3\|lpm_add_sub:add_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[27\] 28 COMB LC4_F35 2 " "Info: 28: + IC(0.000 ns) + CELL(0.200 ns) = 8.500 ns; Loc. = LC4_F35; Fanout = 2; COMB Node = 'div_clk:inst3\|lpm_add_sub:add_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[27\]'" {  } { { "F:/verilog/jingshai/key_scan1/db/key_scan1_cmp.qrpt" "" { Report "F:/verilog/jingshai/key_scan1/db/key_scan1_cmp.qrpt" Compiler "key_scan1" "UNKNOWN" "V1" "F:/verilog/jingshai/key_scan1/db/key_scan1.quartus_db" { Floorplan "F:/verilog/jingshai/key_scan1/" "" "0.200 ns" { div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[26] div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[27] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quar5.0/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 8.700 ns div_clk:inst3\|lpm_add_sub:add_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[28\] 29 COMB LC5_F35 2 " "Info: 29: + IC(0.000 ns) + CELL(0.200 ns) = 8.700 ns; Loc. = LC5_F35; Fanout = 2; COMB Node = 'div_clk:inst3\|lpm_add_sub:add_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[28\]'" {  } { { "F:/verilog/jingshai/key_scan1/db/key_scan1_cmp.qrpt" "" { Report "F:/verilog/jingshai/key_scan1/db/key_scan1_cmp.qrpt" Compiler "key_scan1" "UNKNOWN" "V1" "F:/verilog/jingshai/key_scan1/db/key_scan1.quartus_db" { Floorplan "F:/verilog/jingshai/key_scan1/" "" "0.200 ns" { div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[27] div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[28] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quar5.0/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 8.900 ns div_clk:inst3\|lpm_add_sub:add_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[29\] 30 COMB LC6_F35 2 " "Info: 30: + IC(0.000 ns) + CELL(0.200 ns) = 8.900 ns; Loc. = LC6_F35; Fanout = 2; COMB Node = 'div_clk:inst3\|lpm_add_sub:add_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[29\]'" {  } { { "F:/verilog/jingshai/key_scan1/db/key_scan1_cmp.qrpt" "" { Report "F:/verilog/jingshai/key_scan1/db/key_scan1_cmp.qrpt" Compiler "key_scan1" "UNKNOWN" "V1" "F:/verilog/jingshai/key_scan1/db/key_scan1.quartus_db" { Floorplan "F:/verilog/jingshai/key_scan1/" "" "0.200 ns" { div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[28] div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[29] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quar5.0/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 9.100 ns div_clk:inst3\|lpm_add_sub:add_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[30\] 31 COMB LC7_F35 1 " "Info: 31: + IC(0.000 ns) + CELL(0.200 ns) = 9.100 ns; Loc. = LC7_F35; Fanout = 1; COMB Node = 'div_clk:inst3\|lpm_add_sub:add_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[30\]'" {  } { { "F:/verilog/jingshai/key_scan1/db/key_scan1_cmp.qrpt" "" { Report "F:/verilog/jingshai/key_scan1/db/key_scan1_cmp.qrpt" Compiler "key_scan1" "UNKNOWN" "V1" "F:/verilog/jingshai/key_scan1/db/key_scan1.quartus_db" { Floorplan "F:/verilog/jingshai/key_scan1/" "" "0.200 ns" { div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[29] div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[30] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quar5.0/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.400 ns) 10.500 ns div_clk:inst3\|lpm_add_sub:add_rtl_1\|addcore:adder\|unreg_res_node\[31\] 32 COMB LC8_F35 1 " "Info: 32: + IC(0.000 ns) + CELL(1.400 ns) = 10.500 ns; Loc. = LC8_F35; Fanout = 1; COMB Node = 'div_clk:inst3\|lpm_add_sub:add_rtl_1\|addcore:adder\|unreg_res_node\[31\]'" {  } { { "F:/verilog/jingshai/key_scan1/db/key_scan1_cmp.qrpt" "" { Report "F:/verilog/jingshai/key_scan1/db/key_scan1_cmp.qrpt" Compiler "key_scan1" "UNKNOWN" "V1" "F:/verilog/jingshai/key_scan1/db/key_scan1.quartus_db" { Floorplan "F:/verilog/jingshai/key_scan1/" "" "1.400 ns" { div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[30] div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|unreg_res_node[31] } "NODE_NAME" } "" } } { "addcore.tdf" "" { Text "d:/altera/quar5.0/libraries/megafunctions/addcore.tdf" 95 16 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(0.800 ns) 12.300 ns div_clk:inst3\|k\[31\] 33 REG LC7_F34 2 " "Info: 33: + IC(1.000 ns) + CELL(0.800 ns) = 12.300 ns; Loc. = LC7_F34; Fanout = 2; REG Node = 'div_clk:inst3\|k\[31\]'" {  } { { "F:/verilog/jingshai/key_scan1/db/key_scan1_cmp.qrpt" "" { Report "F:/verilog/jingshai/key_scan1/db/key_scan1_cmp.qrpt" Compiler "key_scan1" "UNKNOWN" "V1" "F:/verilog/jingshai/key_scan1/db/key_scan1.quartus_db" { Floorplan "F:/verilog/jingshai/key_scan1/" "" "1.800 ns" { div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|unreg_res_node[31] div_clk:inst3|k[31] } "NODE_NAME" } "" } } { "div_clk.v" "" { Text "F:/verilog/jingshai/key_scan1/div_clk.v" 11 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.700 ns 70.73 % " "Info: Total cell delay = 8.700 ns ( 70.73 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.600 ns 29.27 % " "Info: Total interconnect delay = 3.600 ns ( 29.27 % )" {  } {  } 0}  } { { "F:/verilog/jingshai/key_scan1/db/key_scan1_cmp.qrpt" "" { Report "F:/verilog/jingshai/key_scan1/db/key_scan1_cmp.qrpt" Compiler "key_scan1" "UNKNOWN" "V1" "F:/verilog/jingshai/key_scan1/db/key_scan1.quartus_db" { Floorplan "F:/verilog/jingshai/key_scan1/" "" "12.300 ns" { div_clk:inst3|k[1] div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[1] div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[2] div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[3] div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[4] div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[5] div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[6] div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[7] div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[8] div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[9] div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[10] div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[11] div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[12] div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[13] div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[14] div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[15] div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[16] div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[17] div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[18] div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[19] div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[20] div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[21] div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[22] div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[23] div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[24] div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[25] div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[26] div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[27] div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[28] div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[29] div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[30] div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|unreg_res_node[31] div_clk:inst3|k[31] } "NODE_NAME" } "" } } { "d:/altera/quar5.0/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quar5.0/bin/Technology_Viewer.qrui" "12.300 ns" { div_clk:inst3|k[1] div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[1] div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[2] div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[3] div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[4] div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[5] div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[6] div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[7] div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[8] div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[9] div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[10] div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[11] div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[12] div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[13] div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[14] div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[15] div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[16] div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[17] div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[18] div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[19] div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[20] div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[21] div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[22] div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[23] div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[24] div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[25] div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[26] div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[27] div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[28] div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[29] div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[30] div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|unreg_res_node[31] div_clk:inst3|k[31] } { 0.000ns 1.100ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.500ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.500ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.500ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 1.000ns } { 0.000ns 0.700ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 1.400ns 0.800ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_in destination 6.400 ns + Shortest register " "Info: + Shortest clock path from clock \"clk_in\" to destination register is 6.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns clk_in 1 CLK PIN_183 33 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_183; Fanout = 33; CLK Node = 'clk_in'" {  } { { "F:/verilog/jingshai/key_scan1/db/key_scan1_cmp.qrpt" "" { Report "F:/verilog/jingshai/key_scan1/db/key_scan1_cmp.qrpt" Compiler "key_scan1" "UNKNOWN" "V1" "F:/verilog/jingshai/key_scan1/db/key_scan1.quartus_db" { Floorplan "F:/verilog/jingshai/key_scan1/" "" "" { clk_in } "NODE_NAME" } "" } } { "key_scan1.bdf" "" { Schematic "F:/verilog/jingshai/key_scan1/key_scan1.bdf" { { 0 304 472 16 "clk_in" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.500 ns) 2.900 ns div_clk:inst3\|clk_200hz 2 REG LC1_E1 45 " "Info: 2: + IC(0.400 ns) + CELL(0.500 ns) = 2.900 ns; Loc. = LC1_E1; Fanout = 45; REG Node = 'div_clk:inst3\|clk_200hz'" {  } { { "F:/verilog/jingshai/key_scan1/db/key_scan1_cmp.qrpt" "" { Report "F:/verilog/jingshai/key_scan1/db/key_scan1_cmp.qrpt" Compiler "key_scan1" "UNKNOWN" "V1" "F:/verilog/jingshai/key_scan1/db/key_scan1.quartus_db" { Floorplan "F:/verilog/jingshai/key_scan1/" "" "0.900 ns" { clk_in div_clk:inst3|clk_200hz } "NODE_NAME" } "" } } { "div_clk.v" "" { Text "F:/verilog/jingshai/key_scan1/div_clk.v" 3 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.500 ns) + CELL(0.000 ns) 6.400 ns div_clk:inst3\|k\[31\] 3 REG LC7_F34 2 " "Info: 3: + IC(3.500 ns) + CELL(0.000 ns) = 6.400 ns; Loc. = LC7_F34; Fanout = 2; REG Node = 'div_clk:inst3\|k\[31\]'" {  } { { "F:/verilog/jingshai/key_scan1/db/key_scan1_cmp.qrpt" "" { Report "F:/verilog/jingshai/key_scan1/db/key_scan1_cmp.qrpt" Compiler "key_scan1" "UNKNOWN" "V1" "F:/verilog/jingshai/key_scan1/db/key_scan1.quartus_db" { Floorplan "F:/verilog/jingshai/key_scan1/" "" "3.500 ns" { div_clk:inst3|clk_200hz div_clk:inst3|k[31] } "NODE_NAME" } "" } } { "div_clk.v" "" { Text "F:/verilog/jingshai/key_scan1/div_clk.v" 11 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.500 ns 39.06 % " "Info: Total cell delay = 2.500 ns ( 39.06 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.900 ns 60.94 % " "Info: Total interconnect delay = 3.900 ns ( 60.94 % )" {  } {  } 0}  } { { "F:/verilog/jingshai/key_scan1/db/key_scan1_cmp.qrpt" "" { Report "F:/verilog/jingshai/key_scan1/db/key_scan1_cmp.qrpt" Compiler "key_scan1" "UNKNOWN" "V1" "F:/verilog/jingshai/key_scan1/db/key_scan1.quartus_db" { Floorplan "F:/verilog/jingshai/key_scan1/" "" "6.400 ns" { clk_in div_clk:inst3|clk_200hz div_clk:inst3|k[31] } "NODE_NAME" } "" } } { "d:/altera/quar5.0/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quar5.0/bin/Technology_Viewer.qrui" "6.400 ns" { clk_in clk_in~out div_clk:inst3|clk_200hz div_clk:inst3|k[31] } { 0.000ns 0.000ns 0.400ns 3.500ns } { 0.000ns 2.000ns 0.500ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_in source 6.400 ns - Longest register " "Info: - Longest clock path from clock \"clk_in\" to source register is 6.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns clk_in 1 CLK PIN_183 33 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_183; Fanout = 33; CLK Node = 'clk_in'" {  } { { "F:/verilog/jingshai/key_scan1/db/key_scan1_cmp.qrpt" "" { Report "F:/verilog/jingshai/key_scan1/db/key_scan1_cmp.qrpt" Compiler "key_scan1" "UNKNOWN" "V1" "F:/verilog/jingshai/key_scan1/db/key_scan1.quartus_db" { Floorplan "F:/verilog/jingshai/key_scan1/" "" "" { clk_in } "NODE_NAME" } "" } } { "key_scan1.bdf" "" { Schematic "F:/verilog/jingshai/key_scan1/key_scan1.bdf" { { 0 304 472 16 "clk_in" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.500 ns) 2.900 ns div_clk:inst3\|clk_200hz 2 REG LC1_E1 45 " "Info: 2: + IC(0.400 ns) + CELL(0.500 ns) = 2.900 ns; Loc. = LC1_E1; Fanout = 45; REG Node = 'div_clk:inst3\|clk_200hz'" {  } { { "F:/verilog/jingshai/key_scan1/db/key_scan1_cmp.qrpt" "" { Report "F:/verilog/jingshai/key_scan1/db/key_scan1_cmp.qrpt" Compiler "key_scan1" "UNKNOWN" "V1" "F:/verilog/jingshai/key_scan1/db/key_scan1.quartus_db" { Floorplan "F:/verilog/jingshai/key_scan1/" "" "0.900 ns" { clk_in div_clk:inst3|clk_200hz } "NODE_NAME" } "" } } { "div_clk.v" "" { Text "F:/verilog/jingshai/key_scan1/div_clk.v" 3 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.500 ns) + CELL(0.000 ns) 6.400 ns div_clk:inst3\|k\[1\] 3 REG LC1_F30 3 " "Info: 3: + IC(3.500 ns) + CELL(0.000 ns) = 6.400 ns; Loc. = LC1_F30; Fanout = 3; REG Node = 'div_clk:inst3\|k\[1\]'" {  } { { "F:/verilog/jingshai/key_scan1/db/key_scan1_cmp.qrpt" "" { Report "F:/verilog/jingshai/key_scan1/db/key_scan1_cmp.qrpt" Compiler "key_scan1" "UNKNOWN" "V1" "F:/verilog/jingshai/key_scan1/db/key_scan1.quartus_db" { Floorplan "F:/verilog/jingshai/key_scan1/" "" "3.500 ns" { div_clk:inst3|clk_200hz div_clk:inst3|k[1] } "NODE_NAME" } "" } } { "div_clk.v" "" { Text "F:/verilog/jingshai/key_scan1/div_clk.v" 11 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.500 ns 39.06 % " "Info: Total cell delay = 2.500 ns ( 39.06 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.900 ns 60.94 % " "Info: Total interconnect delay = 3.900 ns ( 60.94 % )" {  } {  } 0}  } { { "F:/verilog/jingshai/key_scan1/db/key_scan1_cmp.qrpt" "" { Report "F:/verilog/jingshai/key_scan1/db/key_scan1_cmp.qrpt" Compiler "key_scan1" "UNKNOWN" "V1" "F:/verilog/jingshai/key_scan1/db/key_scan1.quartus_db" { Floorplan "F:/verilog/jingshai/key_scan1/" "" "6.400 ns" { clk_in div_clk:inst3|clk_200hz div_clk:inst3|k[1] } "NODE_NAME" } "" } } { "d:/altera/quar5.0/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quar5.0/bin/Technology_Viewer.qrui" "6.400 ns" { clk_in clk_in~out div_clk:inst3|clk_200hz div_clk:inst3|k[1] } { 0.000ns 0.000ns 0.400ns 3.500ns } { 0.000ns 2.000ns 0.500ns 0.000ns } } }  } 0}  } { { "F:/verilog/jingshai/key_scan1/db/key_scan1_cmp.qrpt" "" { Report "F:/verilog/jingshai/key_scan1/db/key_scan1_cmp.qrpt" Compiler "key_scan1" "UNKNOWN" "V1" "F:/verilog/jingshai/key_scan1/db/key_scan1.quartus_db" { Floorplan "F:/verilog/jingshai/key_scan1/" "" "6.400 ns" { clk_in div_clk:inst3|clk_200hz div_clk:inst3|k[31] } "NODE_NAME" } "" } } { "d:/altera/quar5.0/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quar5.0/bin/Technology_Viewer.qrui" "6.400 ns" { clk_in clk_in~out div_clk:inst3|clk_200hz div_clk:inst3|k[31] } { 0.000ns 0.000ns 0.400ns 3.500ns } { 0.000ns 2.000ns 0.500ns 0.000ns } } } { "F:/verilog/jingshai/key_scan1/db/key_scan1_cmp.qrpt" "" { Report "F:/verilog/jingshai/key_scan1/db/key_scan1_cmp.qrpt" Compiler "key_scan1" "UNKNOWN" "V1" "F:/verilog/jingshai/key_scan1/db/key_scan1.quartus_db" { Floorplan "F:/verilog/jingshai/key_scan1/" "" "6.400 ns" { clk_in div_clk:inst3|clk_200hz div_clk:inst3|k[1] } "NODE_NAME" } "" } } { "d:/altera/quar5.0/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quar5.0/bin/Technology_Viewer.qrui" "6.400 ns" { clk_in clk_in~out div_clk:inst3|clk_200hz div_clk:inst3|k[1] } { 0.000ns 0.000ns 0.400ns 3.500ns } { 0.000ns 2.000ns 0.500ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.500 ns + " "Info: + Micro clock to output delay of source is 0.500 ns" {  } { { "div_clk.v" "" { Text "F:/verilog/jingshai/key_scan1/div_clk.v" 11 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.600 ns + " "Info: + Micro setup delay of destination is 0.600 ns" {  } { { "div_clk.v" "" { Text "F:/verilog/jingshai/key_scan1/div_clk.v" 11 -1 0 } }  } 0}  } { { "F:/verilog/jingshai/key_scan1/db/key_scan1_cmp.qrpt" "" { Report "F:/verilog/jingshai/key_scan1/db/key_scan1_cmp.qrpt" Compiler "key_scan1" "UNKNOWN" "V1" "F:/verilog/jingshai/key_scan1/db/key_scan1.quartus_db" { Floorplan "F:/verilog/jingshai/key_scan1/" "" "12.300 ns" { div_clk:inst3|k[1] div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[1] div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[2] div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[3] div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[4] div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[5] div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[6] div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[7] div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[8] div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[9] div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[10] div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[11] div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[12] div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[13] div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[14] div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[15] div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[16] div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[17] div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[18] div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[19] div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[20] div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[21] div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[22] div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[23] div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[24] div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[25] div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[26] div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[27] div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[28] div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[29] div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[30] div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|unreg_res_node[31] div_clk:inst3|k[31] } "NODE_NAME" } "" } } { "d:/altera/quar5.0/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quar5.0/bin/Technology_Viewer.qrui" "12.300 ns" { div_clk:inst3|k[1] div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[1] div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[2] div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[3] div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[4] div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[5] div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[6] div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[7] div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[8] div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[9] div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[10] div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[11] div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[12] div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[13] div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[14] div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[15] div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[16] div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[17] div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[18] div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[19] div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[20] div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[21] div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[22] div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[23] div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[24] div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[25] div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[26] div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[27] div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[28] div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[29] div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[30] div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|unreg_res_node[31] div_clk:inst3|k[31] } { 0.000ns 1.100ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.500ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.500ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.500ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 1.000ns } { 0.000ns 0.700ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 1.400ns 0.800ns } } } { "F:/verilog/jingshai/key_scan1/db/key_scan1_cmp.qrpt" "" { Report "F:/verilog/jingshai/key_scan1/db/key_scan1_cmp.qrpt" Compiler "key_scan1" "UNKNOWN" "V1" "F:/verilog/jingshai/key_scan1/db/key_scan1.quartus_db" { Floorplan "F:/verilog/jingshai/key_scan1/" "" "6.400 ns" { clk_in div_clk:inst3|clk_200hz div_clk:inst3|k[31] } "NODE_NAME" } "" } } { "d:/altera/quar5.0/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quar5.0/bin/Technology_Viewer.qrui" "6.400 ns" { clk_in clk_in~out div_clk:inst3|clk_200hz div_clk:inst3|k[31] } { 0.000ns 0.000ns 0.400ns 3.500ns } { 0.000ns 2.000ns 0.500ns 0.000ns } } } { "F:/verilog/jingshai/key_scan1/db/key_scan1_cmp.qrpt" "" { Report "F:/verilog/jingshai/key_scan1/db/key_scan1_cmp.qrpt" Compiler "key_scan1" "UNKNOWN" "V1" "F:/verilog/jingshai/key_scan1/db/key_scan1.quartus_db" { Floorplan "F:/verilog/jingshai/key_scan1/" "" "6.400 ns" { clk_in div_clk:inst3|clk_200hz div_clk:inst3|k[1] } "NODE_NAME" } "" } } { "d:/altera/quar5.0/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quar5.0/bin/Technology_Viewer.qrui" "6.400 ns" { clk_in clk_in~out div_clk:inst3|clk_200hz div_clk:inst3|k[1] } { 0.000ns 0.000ns 0.400ns 3.500ns } { 0.000ns 2.000ns 0.500ns 0.000ns } } }  } 0}
{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "clk_in 27 " "Warning: Circuit may not operate. Detected 27 non-operational path(s) clocked by clock \"clk_in\" with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0}
{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "qudou:6\|d:18\|q key_scan:inst\|retn_out\[0\] clk_in 2.9 ns " "Info: Found hold time violation between source  pin or register \"qudou:6\|d:18\|q\" and destination pin or register \"key_scan:inst\|retn_out\[0\]\" for clock \"clk_in\" (Hold time is 2.9 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "3.400 ns + Largest " "Info: + Largest clock skew is 3.400 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_in destination 9.800 ns + Longest register " "Info: + Longest clock path from clock \"clk_in\" to destination register is 9.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns clk_in 1 CLK PIN_183 33 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_183; Fanout = 33; CLK Node = 'clk_in'" {  } { { "F:/verilog/jingshai/key_scan1/db/key_scan1_cmp.qrpt" "" { Report "F:/verilog/jingshai/key_scan1/db/key_scan1_cmp.qrpt" Compiler "key_scan1" "UNKNOWN" "V1" "F:/verilog/jingshai/key_scan1/db/key_scan1.quartus_db" { Floorplan "F:/verilog/jingshai/key_scan1/" "" "" { clk_in } "NODE_NAME" } "" } } { "key_scan1.bdf" "" { Schematic "F:/verilog/jingshai/key_scan1/key_scan1.bdf" { { 0 304 472 16 "clk_in" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.500 ns) 2.900 ns div_clk:inst3\|clk_200hz 2 REG LC1_E1 45 " "Info: 2: + IC(0.400 ns) + CELL(0.500 ns) = 2.900 ns; Loc. = LC1_E1; Fanout = 45; REG Node = 'div_clk:inst3\|clk_200hz'" {  } { { "F:/verilog/jingshai/key_scan1/db/key_scan1_cmp.qrpt" "" { Report "F:/verilog/jingshai/key_scan1/db/key_scan1_cmp.qrpt" Compiler "key_scan1" "UNKNOWN" "V1" "F:/verilog/jingshai/key_scan1/db/key_scan1.quartus_db" { Floorplan "F:/verilog/jingshai/key_scan1/" "" "0.900 ns" { clk_in div_clk:inst3|clk_200hz } "NODE_NAME" } "" } } { "div_clk.v" "" { Text "F:/verilog/jingshai/key_scan1/div_clk.v" 3 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.500 ns) + CELL(0.500 ns) 6.900 ns div_clk:inst3\|clk_scan 3 REG LC5_F28 5 " "Info: 3: + IC(3.500 ns) + CELL(0.500 ns) = 6.900 ns; Loc. = LC5_F28; Fanout = 5; REG Node = 'div_clk:inst3\|clk_scan'" {  } { { "F:/verilog/jingshai/key_scan1/db/key_scan1_cmp.qrpt" "" { Report "F:/verilog/jingshai/key_scan1/db/key_scan1_cmp.qrpt" Compiler "key_scan1" "UNKNOWN" "V1" "F:/verilog/jingshai/key_scan1/db/key_scan1.quartus_db" { Floorplan "F:/verilog/jingshai/key_scan1/" "" "4.000 ns" { div_clk:inst3|clk_200hz div_clk:inst3|clk_scan } "NODE_NAME" } "" } } { "div_clk.v" "" { Text "F:/verilog/jingshai/key_scan1/div_clk.v" 3 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.900 ns) + CELL(0.000 ns) 9.800 ns key_scan:inst\|retn_out\[0\] 4 REG LC2_D10 3 " "Info: 4: + IC(2.900 ns) + CELL(0.000 ns) = 9.800 ns; Loc. = LC2_D10; Fanout = 3; REG Node = 'key_scan:inst\|retn_out\[0\]'" {  } { { "F:/verilog/jingshai/key_scan1/db/key_scan1_cmp.qrpt" "" { Report "F:/verilog/jingshai/key_scan1/db/key_scan1_cmp.qrpt" Compiler "key_scan1" "UNKNOWN" "V1" "F:/verilog/jingshai/key_scan1/db/key_scan1.quartus_db" { Floorplan "F:/verilog/jingshai/key_scan1/" "" "2.900 ns" { div_clk:inst3|clk_scan key_scan:inst|retn_out[0] } "NODE_NAME" } "" } } { "key_scan.v" "" { Text "F:/verilog/jingshai/key_scan1/key_scan.v" 14 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns 30.61 % " "Info: Total cell delay = 3.000 ns ( 30.61 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.800 ns 69.39 % " "Info: Total interconnect delay = 6.800 ns ( 69.39 % )" {  } {  } 0}  } { { "F:/verilog/jingshai/key_scan1/db/key_scan1_cmp.qrpt" "" { Report "F:/verilog/jingshai/key_scan1/db/key_scan1_cmp.qrpt" Compiler "key_scan1" "UNKNOWN" "V1" "F:/verilog/jingshai/key_scan1/db/key_scan1.quartus_db" { Floorplan "F:/verilog/jingshai/key_scan1/" "" "9.800 ns" { clk_in div_clk:inst3|clk_200hz div_clk:inst3|clk_scan key_scan:inst|retn_out[0] } "NODE_NAME" } "" } } { "d:/altera/quar5.0/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quar5.0/bin/Technology_Viewer.qrui" "9.800 ns" { clk_in clk_in~out div_clk:inst3|clk_200hz div_clk:inst3|clk_scan key_scan:inst|retn_out[0] } { 0.0ns 0.0ns 0.4ns 3.5ns 2.9ns } { 0.0ns 2.0ns 0.5ns 0.5ns 0.0ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_in source 6.400 ns - Shortest register " "Info: - Shortest clock path from clock \"clk_in\" to source register is 6.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns clk_in 1 CLK PIN_183 33 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_183; Fanout = 33; CLK Node = 'clk_in'" {  } { { "F:/verilog/jingshai/key_scan1/db/key_scan1_cmp.qrpt" "" { Report "F:/verilog/jingshai/key_scan1/db/key_scan1_cmp.qrpt" Compiler "key_scan1" "UNKNOWN" "V1" "F:/verilog/jingshai/key_scan1/db/key_scan1.quartus_db" { Floorplan "F:/verilog/jingshai/key_scan1/" "" "" { clk_in } "NODE_NAME" } "" } } { "key_scan1.bdf" "" { Schematic "F:/verilog/jingshai/key_scan1/k