key_scan1.tan.qmsg

用verilog实现的四乘四键盘程序,在Quartus II上编译通过并成功

{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "key_scan:inst\|qout\[0\] " "Info: Node \"key_scan:inst\|qout\[0\]\"" {  } { { "key_scan.v" "" { Text "F:/verilog/jingshai/key_scan1/key_scan.v" 8 -1 0 } }  } 0}  } { { "key_scan.v" "" { Text "F:/verilog/jingshai/key_scan1/key_scan.v" 8 -1 0 } }  } 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk_in " "Info: Assuming node \"clk_in\" is an undefined clock" {  } { { "key_scan1.bdf" "" { Schematic "F:/verilog/jingshai/key_scan1/key_scan1.bdf" { { 0 304 472 16 "clk_in" "" } } } } { "d:/altera/quar5.0/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quar5.0/bin/Assignment Editor.qase" 1 { { 0 "clk_in" } } } }  } 0}  } {  } 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "12 " "Warning: Found 12 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "qudou:13\|d:17\|q " "Info: Detected ripple clock \"qudou:13\|d:17\|q\" as buffer" {  } { { "d.v" "" { Text "F:/verilog/jingshai/key_scan1/d.v" 4 -1 0 } } { "d:/altera/quar5.0/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quar5.0/bin/Assignment Editor.qase" 1 { { 0 "qudou:13\|d:17\|q" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "qudou:13\|d:18\|q " "Info: Detected ripple clock \"qudou:13\|d:18\|q\" as buffer" {  } { { "d.v" "" { Text "F:/verilog/jingshai/key_scan1/d.v" 4 -1 0 } } { "d:/altera/quar5.0/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quar5.0/bin/Assignment Editor.qase" 1 { { 0 "qudou:13\|d:18\|q" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "qudou:11\|d:17\|q " "Info: Detected ripple clock \"qudou:11\|d:17\|q\" as buffer" {  } { { "d.v" "" { Text "F:/verilog/jingshai/key_scan1/d.v" 4 -1 0 } } { "d:/altera/quar5.0/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quar5.0/bin/Assignment Editor.qase" 1 { { 0 "qudou:11\|d:17\|q" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "qudou:11\|d:18\|q " "Info: Detected ripple clock \"qudou:11\|d:18\|q\" as buffer" {  } { { "d.v" "" { Text "F:/verilog/jingshai/key_scan1/d.v" 4 -1 0 } } { "d:/altera/quar5.0/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quar5.0/bin/Assignment Editor.qase" 1 { { 0 "qudou:11\|d:18\|q" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "qudou:10\|d:17\|q " "Info: Detected ripple clock \"qudou:10\|d:17\|q\" as buffer" {  } { { "d.v" "" { Text "F:/verilog/jingshai/key_scan1/d.v" 4 -1 0 } } { "d:/altera/quar5.0/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quar5.0/bin/Assignment Editor.qase" 1 { { 0 "qudou:10\|d:17\|q" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "qudou:10\|d:18\|q " "Info: Detected ripple clock \"qudou:10\|d:18\|q\" as buffer" {  } { { "d.v" "" { Text "F:/verilog/jingshai/key_scan1/d.v" 4 -1 0 } } { "d:/altera/quar5.0/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quar5.0/bin/Assignment Editor.qase" 1 { { 0 "qudou:10\|d:18\|q" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "qudou:6\|d:17\|q " "Info: Detected ripple clock \"qudou:6\|d:17\|q\" as buffer" {  } { { "d.v" "" { Text "F:/verilog/jingshai/key_scan1/d.v" 4 -1 0 } } { "d:/altera/quar5.0/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quar5.0/bin/Assignment Editor.qase" 1 { { 0 "qudou:6\|d:17\|q" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "qudou:6\|d:18\|q " "Info: Detected ripple clock \"qudou:6\|d:18\|q\" as buffer" {  } { { "d.v" "" { Text "F:/verilog/jingshai/key_scan1/d.v" 4 -1 0 } } { "d:/altera/quar5.0/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quar5.0/bin/Assignment Editor.qase" 1 { { 0 "qudou:6\|d:18\|q" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "key_scan:inst\|reduce_nor~16 " "Info: Detected gated clock \"key_scan:inst\|reduce_nor~16\" as buffer" {  } { { "d:/altera/quar5.0/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quar5.0/bin/Assignment Editor.qase" 1 { { 0 "key_scan:inst\|reduce_nor~16" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "key_scan:inst\|reduce_nor~15 " "Info: Detected gated clock \"key_scan:inst\|reduce_nor~15\" as buffer" {  } { { "d:/altera/quar5.0/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quar5.0/bin/Assignment Editor.qase" 1 { { 0 "key_scan:inst\|reduce_nor~15" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "div_clk:inst3\|clk_scan " "Info: Detected ripple clock \"div_clk:inst3\|clk_scan\" as buffer" {  } { { "div_clk.v" "" { Text "F:/verilog/jingshai/key_scan1/div_clk.v" 3 -1 0 } } { "d:/altera/quar5.0/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quar5.0/bin/Assignment Editor.qase" 1 { { 0 "div_clk:inst3\|clk_scan" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "div_clk:inst3\|clk_200hz " "Info: Detected ripple clock \"div_clk:inst3\|clk_200hz\" as buffer" {  } { { "div_clk.v" "" { Text "F:/verilog/jingshai/key_scan1/div_clk.v" 3 -1 0 } } { "d:/altera/quar5.0/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quar5.0/bin/Assignment Editor.qase" 1 { { 0 "div_clk:inst3\|clk_200hz" } } } }  } 0}  } {  } 0}