key_scan1.tan.qmsg

用verilog实现的四乘四键盘程序,在Quartus II上编译通过并成功

{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Warning" "WTAN_FOUND_COMB_LATCHES" "" "Warning: Timing Analysis found one or more latches implemented as combinational loops" { { "Warning" "WTAN_COMB_LATCH_NODE" "key_scan:inst\|qout\[0\] " "Warning: Node \"key_scan:inst\|qout\[0\]\" is a latch" {  } { { "key_scan.v" "" { Text "F:/verilog/jingshai/key_scan1/key_scan.v" 8 -1 0 } }  } 0} { "Warning" "WTAN_COMB_LATCH_NODE" "key_scan:inst\|qout\[1\] " "Warning: Node \"key_scan:inst\|qout\[1\]\" is a latch" {  } { { "key_scan.v" "" { Text "F:/verilog/jingshai/key_scan1/key_scan.v" 8 -1 0 } }  } 0} { "Warning" "WTAN_COMB_LATCH_NODE" "key_scan:inst\|qout\[2\] " "Warning: Node \"key_scan:inst\|qout\[2\]\" is a latch" {  } { { "key_scan.v" "" { Text "F:/verilog/jingshai/key_scan1/key_scan.v" 8 -1 0 } }  } 0} { "Warning" "WTAN_COMB_LATCH_NODE" "key_scan:inst\|qout\[3\] " "Warning: Node \"key_scan:inst\|qout\[3\]\" is a latch" {  } { { "key_scan.v" "" { Text "F:/verilog/jingshai/key_scan1/key_scan.v" 8 -1 0 } }  } 0}  } {  } 0}