📄 key_scan1.rpt
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Device-Specific Information: f:\verilog\竞赛\key_scan1\key_scan1.rpt
key_scan1
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 4 clk_scan
Device-Specific Information: f:\verilog\竞赛\key_scan1\key_scan1.rpt
key_scan1
** EQUATIONS **
clk_scan : INPUT;
retn_in0 : INPUT;
retn_in1 : INPUT;
retn_in2 : INPUT;
retn_in3 : INPUT;
-- Node name is 'int'
-- Equation name is 'int', type is output
int = _LC2_A40;
-- Node name is 'qout0'
-- Equation name is 'qout0', type is output
qout0 = _LC3_A40;
-- Node name is 'qout1'
-- Equation name is 'qout1', type is output
qout1 = _LC4_A40;
-- Node name is 'qout2'
-- Equation name is 'qout2', type is output
qout2 = _LC3_A48;
-- Node name is 'qout3'
-- Equation name is 'qout3', type is output
qout3 = _LC8_A48;
-- Node name is ':32' = 'q0'
-- Equation name is 'q0', location is LC7_A48, type is buried.
q0 = DFFE(!q0, GLOBAL( clk_scan), VCC, VCC, _LC2_A40);
-- Node name is ':31' = 'q1'
-- Equation name is 'q1', location is LC1_A40, type is buried.
q1 = DFFE( _EQ001, GLOBAL( clk_scan), VCC, VCC, _LC2_A40);
_EQ001 = q0 & !q1
# !q0 & q1;
-- Node name is ':132' = 'retn_out0'
-- Equation name is 'retn_out0', location is LC6_A40, type is buried.
retn_out0 = DFFE( _EQ002, GLOBAL( clk_scan), VCC, VCC, VCC);
_EQ002 = _LC2_A40 & retn_out0
# !_LC2_A40 & _LC5_A40 & retn_in0;
-- Node name is ':131' = 'retn_out1'
-- Equation name is 'retn_out1', location is LC8_A40, type is buried.
retn_out1 = DFFE( _EQ003, GLOBAL( clk_scan), VCC, VCC, VCC);
_EQ003 = !_LC2_A40 & _LC7_A40 & retn_in0
# _LC2_A40 & retn_out1;
-- Node name is 'scan_out0'
-- Equation name is 'scan_out0', type is output
scan_out0 = _LC1_A48;
-- Node name is 'scan_out1'
-- Equation name is 'scan_out1', type is output
scan_out1 = _LC6_A48;
-- Node name is 'scan_out2'
-- Equation name is 'scan_out2', type is output
scan_out2 = _LC4_A48;
-- Node name is 'scan_out3'
-- Equation name is 'scan_out3', type is output
scan_out3 = _LC2_A48;
-- Node name is ':25'
-- Equation name is '_LC2_A40', type is buried
_LC2_A40 = LCELL( _EQ004);
_EQ004 = retn_in0 & retn_in1 & retn_in2 & retn_in3;
-- Node name is ':73'
-- Equation name is '_LC2_A48', type is buried
_LC2_A48 = LCELL( _EQ005);
_EQ005 = !q1
# !q0;
-- Node name is ':74'
-- Equation name is '_LC4_A48', type is buried
_LC4_A48 = LCELL( _EQ006);
_EQ006 = !q1
# q0;
-- Node name is ':75'
-- Equation name is '_LC6_A48', type is buried
_LC6_A48 = LCELL( _EQ007);
_EQ007 = !q0
# q1;
-- Node name is ':76'
-- Equation name is '_LC1_A48', type is buried
_LC1_A48 = LCELL( _EQ008);
_EQ008 = q0
# q1;
-- Node name is ':122'
-- Equation name is '_LC5_A40', type is buried
_LC5_A40 = LCELL( _EQ009);
_EQ009 = !retn_in1
# retn_in2 & retn_out0
# retn_in2 & !retn_in3;
-- Node name is '~127~1'
-- Equation name is '~127~1', location is LC7_A40, type is buried.
-- synthesized logic cell
_LC7_A40 = LCELL( _EQ010);
_EQ010 = retn_in1 & retn_out1
# retn_in1 & !retn_in2
# retn_in1 & !retn_in3;
-- Node name is ':137'
-- Equation name is '_LC8_A48', type is buried
_LC8_A48 = LCELL( _EQ011);
_EQ011 = _LC2_A40 & _LC8_A48
# !_LC2_A40 & q1;
-- Node name is ':138'
-- Equation name is '_LC3_A48', type is buried
_LC3_A48 = LCELL( _EQ012);
_EQ012 = _LC2_A40 & _LC3_A48
# !_LC2_A40 & q0;
-- Node name is ':139'
-- Equation name is '_LC4_A40', type is buried
_LC4_A40 = LCELL( _EQ013);
_EQ013 = _LC2_A40 & _LC4_A40
# !_LC2_A40 & retn_out1;
-- Node name is ':140'
-- Equation name is '_LC3_A40', type is buried
_LC3_A40 = LCELL( _EQ014);
_EQ014 = _LC2_A40 & _LC3_A40
# !_LC2_A40 & retn_out0;
Project Information f:\verilog\竞赛\key_scan1\key_scan1.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'ACEX1K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:05
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:06
Memory Allocated
-----------------
Peak memory allocated during compilation = 122,623K
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