key_scan1.map.eqn

用verilog实现的四乘四键盘程序,在Quartus II上编译通过并成功

--J1L431Q is div_clk:inst3|k[29]~335
--operation mode is normal

J1L431Q = J1_k[29];


--J1_k[28] is div_clk:inst3|k[28]
--operation mode is normal

J1_k[28]_lut_out = P6_cs_buffer[28];
J1_k[28] = DFFEA(J1_k[28]_lut_out, J1_clk_200hz, rst, , , , );

--J1L231Q is div_clk:inst3|k[28]~336
--operation mode is normal

J1L231Q = J1_k[28];


--J1_k[27] is div_clk:inst3|k[27]
--operation mode is normal

J1_k[27]_lut_out = P6_cs_buffer[27];
J1_k[27] = DFFEA(J1_k[27]_lut_out, J1_clk_200hz, rst, , , , );

--J1L031Q is div_clk:inst3|k[27]~337
--operation mode is normal

J1L031Q = J1_k[27];


--J1L351 is div_clk:inst3|reduce_nor~644
--operation mode is normal

J1L351 = (!J1_k[30] & !J1_k[29] & !J1_k[28] & !J1_k[27]) & CASCADE(J1L271);

--J1L371 is div_clk:inst3|reduce_nor~672
--operation mode is normal

J1L371 = (!J1_k[30] & !J1_k[29] & !J1_k[28] & !J1_k[27]) & CASCADE(J1L271);


--J1_k[18] is div_clk:inst3|k[18]
--operation mode is normal

J1_k[18]_lut_out = P6_cs_buffer[18];
J1_k[18] = DFFEA(J1_k[18]_lut_out, J1_clk_200hz, rst, , , , );

--J1L211Q is div_clk:inst3|k[18]~338
--operation mode is normal

J1L211Q = J1_k[18];


--J1_k[17] is div_clk:inst3|k[17]
--operation mode is normal

J1_k[17]_lut_out = P6_cs_buffer[17];
J1_k[17] = DFFEA(J1_k[17]_lut_out, J1_clk_200hz, rst, , , , );

--J1L011Q is div_clk:inst3|k[17]~339
--operation mode is normal

J1L011Q = J1_k[17];


--J1_k[16] is div_clk:inst3|k[16]
--operation mode is normal

J1_k[16]_lut_out = P6_cs_buffer[16];
J1_k[16] = DFFEA(J1_k[16]_lut_out, J1_clk_200hz, rst, , , , );

--J1L801Q is div_clk:inst3|k[16]~340
--operation mode is normal

J1L801Q = J1_k[16];


--J1_k[15] is div_clk:inst3|k[15]
--operation mode is normal

J1_k[15]_lut_out = P6_cs_buffer[15];
J1_k[15] = DFFEA(J1_k[15]_lut_out, J1_clk_200hz, rst, , , , );

--J1L601Q is div_clk:inst3|k[15]~341
--operation mode is normal

J1L601Q = J1_k[15];


--J1L641 is div_clk:inst3|reduce_nor~634
--operation mode is normal

J1L641 = !J1_k[18] & !J1_k[17] & !J1_k[16] & !J1_k[15];

--J1L471 is div_clk:inst3|reduce_nor~673
--operation mode is normal

J1L471 = !J1_k[18] & !J1_k[17] & !J1_k[16] & !J1_k[15];

--J1L571 is div_clk:inst3|reduce_nor~674
--operation mode is normal

J1L571 = !J1_k[18] & !J1_k[17] & !J1_k[16] & !J1_k[15];


--J1_k[22] is div_clk:inst3|k[22]
--operation mode is normal

J1_k[22]_lut_out = P6_cs_buffer[22];
J1_k[22] = DFFEA(J1_k[22]_lut_out, J1_clk_200hz, rst, , , , );

--J1L021Q is div_clk:inst3|k[22]~342
--operation mode is normal

J1L021Q = J1_k[22];


--J1_k[21] is div_clk:inst3|k[21]
--operation mode is normal

J1_k[21]_lut_out = P6_cs_buffer[21];
J1_k[21] = DFFEA(J1_k[21]_lut_out, J1_clk_200hz, rst, , , , );

--J1L811Q is div_clk:inst3|k[21]~343
--operation mode is normal

J1L811Q = J1_k[21];


--J1_k[20] is div_clk:inst3|k[20]
--operation mode is normal

J1_k[20]_lut_out = P6_cs_buffer[20];
J1_k[20] = DFFEA(J1_k[20]_lut_out, J1_clk_200hz, rst, , , , );

--J1L611Q is div_clk:inst3|k[20]~344
--operation mode is normal

J1L611Q = J1_k[20];


--J1_k[19] is div_clk:inst3|k[19]
--operation mode is normal

J1_k[19]_lut_out = P6_cs_buffer[19];
J1_k[19] = DFFEA(J1_k[19]_lut_out, J1_clk_200hz, rst, , , , );

--J1L411Q is div_clk:inst3|k[19]~345
--operation mode is normal

J1L411Q = J1_k[19];


--J1L451 is div_clk:inst3|reduce_nor~645
--operation mode is normal

J1L451 = (!J1_k[22] & !J1_k[21] & !J1_k[20] & !J1_k[19]) & CASCADE(J1L571);

--J1L671 is div_clk:inst3|reduce_nor~675
--operation mode is normal

J1L671 = (!J1_k[22] & !J1_k[21] & !J1_k[20] & !J1_k[19]) & CASCADE(J1L571);


--J1_k[10] is div_clk:inst3|k[10]
--operation mode is normal

J1_k[10]_lut_out = P6_cs_buffer[10];
J1_k[10] = DFFEA(J1_k[10]_lut_out, J1_clk_200hz, rst, , , , );

--J1L69Q is div_clk:inst3|k[10]~346
--operation mode is normal

J1L69Q = J1_k[10];


--J1_k[9] is div_clk:inst3|k[9]
--operation mode is normal

J1_k[9]_lut_out = P6_cs_buffer[9];
J1_k[9] = DFFEA(J1_k[9]_lut_out, J1_clk_200hz, rst, , , , );

--J1L49Q is div_clk:inst3|k[9]~347
--operation mode is normal

J1L49Q = J1_k[9];


--J1_k[8] is div_clk:inst3|k[8]
--operation mode is normal

J1_k[8]_lut_out = P6_cs_buffer[8];
J1_k[8] = DFFEA(J1_k[8]_lut_out, J1_clk_200hz, rst, , , , );

--J1L29Q is div_clk:inst3|k[8]~348
--operation mode is normal

J1L29Q = J1_k[8];


--J1_k[7] is div_clk:inst3|k[7]
--operation mode is normal

J1_k[7]_lut_out = P6_cs_buffer[7];
J1_k[7] = DFFEA(J1_k[7]_lut_out, J1_clk_200hz, rst, , , , );

--J1L09Q is div_clk:inst3|k[7]~349
--operation mode is normal

J1L09Q = J1_k[7];


--J1L741 is div_clk:inst3|reduce_nor~636
--operation mode is normal

J1L741 = !J1_k[10] & !J1_k[9] & !J1_k[8] & !J1_k[7];

--J1L771 is div_clk:inst3|reduce_nor~676
--operation mode is normal

J1L771 = !J1_k[10] & !J1_k[9] & !J1_k[8] & !J1_k[7];

--J1L871 is div_clk:inst3|reduce_nor~677
--operation mode is normal

J1L871 = !J1_k[10] & !J1_k[9] & !J1_k[8] & !J1_k[7];


--J1_k[14] is div_clk:inst3|k[14]
--operation mode is normal

J1_k[14]_lut_out = P6_cs_buffer[14];
J1_k[14] = DFFEA(J1_k[14]_lut_out, J1_clk_200hz, rst, , , , );

--J1L401Q is div_clk:inst3|k[14]~350
--operation mode is normal

J1L401Q = J1_k[14];


--J1_k[13] is div_clk:inst3|k[13]
--operation mode is normal

J1_k[13]_lut_out = P6_cs_buffer[13];
J1_k[13] = DFFEA(J1_k[13]_lut_out, J1_clk_200hz, rst, , , , );

--J1L201Q is div_clk:inst3|k[13]~351
--operation mode is normal

J1L201Q = J1_k[13];


--J1_k[12] is div_clk:inst3|k[12]
--operation mode is normal

J1_k[12]_lut_out = P6_cs_buffer[12];
J1_k[12] = DFFEA(J1_k[12]_lut_out, J1_clk_200hz, rst, , , , );

--J1L001Q is div_clk:inst3|k[12]~352
--operation mode is normal

J1L001Q = J1_k[12];


--J1_k[11] is div_clk:inst3|k[11]
--operation mode is normal

J1_k[11]_lut_out = P6_cs_buffer[11];
J1_k[11] = DFFEA(J1_k[11]_lut_out, J1_clk_200hz, rst, , , , );

--J1L89Q is div_clk:inst3|k[11]~353
--operation mode is normal

J1L89Q = J1_k[11];


--J1L551 is div_clk:inst3|reduce_nor~646
--operation mode is normal

J1L551 = (!J1_k[14] & !J1_k[13] & !J1_k[12] & !J1_k[11]) & CASCADE(J1L871);

--J1L971 is div_clk:inst3|reduce_nor~678
--operation mode is normal

J1L971 = (!J1_k[14] & !J1_k[13] & !J1_k[12] & !J1_k[11]) & CASCADE(J1L871);


--J1_k[2] is div_clk:inst3|k[2]
--operation mode is normal

J1_k[2]_lut_out = J1L931 & P6_cs_buffer[2];
J1_k[2] = DFFEA(J1_k[2]_lut_out, J1_clk_200hz, rst, , , , );

--J1L08Q is div_clk:inst3|k[2]~354
--operation mode is normal

J1L08Q = J1_k[2];


--J1_k[0] is div_clk:inst3|k[0]
--operation mode is arithmetic

J1_k[0]_lut_out = !J1_k[0];
J1_k[0] = DFFEA(J1_k[0]_lut_out, J1_clk_200hz, rst, , , , );

--J1L67Q is div_clk:inst3|k[0]~355
--operation mode is arithmetic

J1L67Q = J1_k[0];

--P6_cout[0] is div_clk:inst3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[0]
--operation mode is arithmetic

P6_cout[0] = CARRY(!J1_k[0]);


--J1_k[1] is div_clk:inst3|k[1]
--operation mode is normal

J1_k[1]_lut_out = P6_cs_buffer[1];
J1_k[1] = DFFEA(J1_k[1]_lut_out, J1_clk_200hz, rst, , , , );

--J1L87Q is div_clk:inst3|k[1]~356
--operation mode is normal

J1L87Q = J1_k[1];


--J1_k[31] is div_clk:inst3|k[31]
--operation mode is normal

J1_k[31]_lut_out = M2_unreg_res_node[31];
J1_k[31] = DFFEA(J1_k[31]_lut_out, J1_clk_200hz, rst, , , , );

--J1L831Q is div_clk:inst3|k[31]~357
--operation mode is normal

J1L831Q = J1_k[31];


--J1L841 is div_clk:inst3|reduce_nor~638
--operation mode is normal

J1L841 = J1_k[2] & J1_k[0] & !J1_k[1] & !J1_k[31];

--J1L081 is div_clk:inst3|reduce_nor~679
--operation mode is normal

J1L081 = J1_k[2] & J1_k[0] & !J1_k[1] & !J1_k[31];

--J1L181 is div_clk:inst3|reduce_nor~680
--operation mode is normal

J1L181 = J1_k[2] & J1_k[0] & !J1_k[1] & !J1_k[31];


--J1_k[6] is div_clk:inst3|k[6]
--operation mode is normal

J1_k[6]_lut_out = P6_cs_buffer[6];
J1_k[6] = DFFEA(J1_k[6]_lut_out, J1_clk_200hz, rst, , , , );

--J1L88Q is div_clk:inst3|k[6]~358
--operation mode is normal

J1L88Q = J1_k[6];


--J1_k[5] is div_clk:inst3|k[5]
--operation mode is normal

J1_k[5]_lut_out = P6_cs_buffer[5];
J1_k[5] = DFFEA(J1_k[5]_lut_out, J1_clk_200hz, rst, , , , );

--J1L68Q is div_clk:inst3|k[5]~359
--operation mode is normal

J1L68Q = J1_k[5];


--J1_k[4] is div_clk:inst3|k[4]
--operation mode is normal

J1_k[4]_lut_out = P6_cs_buffer[4];
J1_k[4] = DFFEA(J1_k[4]_lut_out, J1_clk_200hz, rst, , , , );

--J1L48Q is div_clk:inst3|k[4]~360
--operation mode is normal

J1L48Q = J1_k[4];


--J1_k[3] is div_clk:inst3|k[3]
--operation mode is normal

J1_k[3]_lut_out = P6_cs_buffer[3];
J1_k[3] = DFFEA(J1_k[3]_lut_out, J1_clk_200hz, rst, , , , );

--J1L28Q is div_clk:inst3|k[3]~361
--operation mode is normal

J1L28Q = J1_k[3];


--J1L651 is div_clk:inst3|reduce_nor~647
--operation mode is normal

J1L651 = (!J1_k[6] & !J1_k[5] & !J1_k[4] & !J1_k[3]) & CASCADE(J1L181);

--J1L281 is div_clk:inst3|reduce_nor~681
--operation mode is normal

J1L281 = (!J1_k[6] & !J1_k[5] & !J1_k[4] & !J1_k[3]) & CASCADE(J1L181);


--K7L2 is qudou:13|d:17|q~9
--operation mode is normal

K7L2 = !K8_q & !K7_q;

--K7L4 is qudou:13|d:17|q~12
--operation mode is normal

K7L4 = !K8_q & !K7_q;


--G1L63 is key_scan:inst|retn_out~161
--operation mode is normal

G1L63 = K6_q & (K7L2 # G1_retn_out[0]) # !K6_q & K5_q & (K7L2 # G1_retn_out[0]);

--G1L83 is key_scan:inst|retn_out~165
--operation mode is normal

G1L83 = K6_q & (K7L2 # G1_retn_out[0]) # !K6_q & K5_q & (K7L2 # G1_retn_out[0]);


--G1L73 is key_scan:inst|retn_out~162
--operation mode is normal

G1L73 = G1L63 # !K4_q & !K3_q;

--G1L93 is key_scan:inst|retn_out~166
--operation mode is normal

G1L93 = G1L63 # !K4_q & !K3_q;


--P3_cs_buffer[27] is div_clk:inst3|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[27]
--operation mode is arithmetic

P3_cs_buffer[27] = J1_i[27] $ (P3_cout[26]);

--P3L78 is div_clk:inst3|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[27]~396
--operation mode is arithmetic

P3L78 = J1_i[27] $ (P3_cout[26]);

--P3_cout[27] is div_clk:inst3|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[27]
--operation mode is arithmetic

P3_cout[27] = CARRY(J1_i[27] & (P3_cout[26]));


--P3_cs_buffer[26] is div_clk:inst3|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[26]
--operation mode is arithmetic

P3_cs_buffer[26] = J1_i[26] $ (P3_cout[25]);

--P3L58 is div_clk:inst3|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[26]~397
--operation mode is arithmetic

P3L58 = J1_i[26] $ (P3_cout[25]);

--P3_cout[26] is div_clk:inst3|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[26]
--operation mode is arithmetic

P3_cout[26] = CARRY(J1_i[26] & (P3_cout[25]));


--P3_cs_buffer[25] is div_clk:inst3|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[25]
--operation mode is arithmetic

P3_cs_buffer[25] = J1_i[25] $ (P3_cout[24]);

--P3L38 is div_clk:inst3|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[25]~398
--operation mode is arithmetic

P3L38 = J1_i[25] $ (P3_cout[24]);

--P3_cout[25] is div_clk:inst3|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[25]
--operation mode is arithmetic

P3_cout[25] = CARRY(J1_i[25] & (P3_cout[24]));


--P3_cs_buffer[24] is div_clk:inst3|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[24]
--operation mode is arithmetic

P3_cs_buffer[24] = J1_i[24] $ (P3_cout[23]);

--P3L18 is div_clk:inst3|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[24]~399
--operation mode is arithmetic

P3L18 = J1_i[24] $ (P3_cout[23]);

--P3_cout[24] is div_clk:inst3|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[24]
--operation mode is arithmetic

P3_cout[24] = CARRY(J1_i[24] & (P3_cout[23]));


--P3_cs_buffer[30] is div_clk:inst3|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[30]
--operation mode is arithmetic

P3_cs_buffer[30] = J1_i[30] $ (P3_cout[29]);

--P3L39 is div_clk:inst3|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[30]~400
--operation mode is arithmetic