key_scan1.map.eqn

用verilog实现的四乘四键盘程序,在Quartus II上编译通过并成功

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-- applicable agreement for further details.
--H1_out[0] is cout6:inst2|out[0]
--operation mode is normal

H1_out[0]_lut_out = !H1_out[0] & (rst);
H1_out[0] = DFFEA(H1_out[0]_lut_out, J1_clk_200hz, , , , , );

--H1L3Q is cout6:inst2|out[0]~110
--operation mode is normal

H1L3Q = H1_out[0];


--H1_out[1] is cout6:inst2|out[1]
--operation mode is normal

H1_out[1]_lut_out = rst & (H1_out[1] & (!H1_out[0]) # !H1_out[1] & !H1_out[2] & H1_out[0]);
H1_out[1] = DFFEA(H1_out[1]_lut_out, J1_clk_200hz, , , , , );

--H1L5Q is cout6:inst2|out[1]~111
--operation mode is normal

H1L5Q = H1_out[1];


--H1_out[2] is cout6:inst2|out[2]
--operation mode is normal

H1_out[2]_lut_out = rst & (H1_out[2] & (!H1_out[0]) # !H1_out[2] & H1_out[1] & H1_out[0]);
H1_out[2] = DFFEA(H1_out[2]_lut_out, J1_clk_200hz, , , , , );

--H1L7Q is cout6:inst2|out[2]~112
--operation mode is normal

H1L7Q = H1_out[2];


--F1L11 is com_digit:54|reduce_or~0
--operation mode is normal

F1L11 = !H1_out[0] & !H1_out[1] # !H1_out[2];

--F1L21 is com_digit:54|reduce_or~4
--operation mode is normal

F1L21 = !H1_out[0] & !H1_out[1] # !H1_out[2];


--F1L1 is com_digit:54|Decoder~55
--operation mode is normal

F1L1 = H1_out[2] & (!H1_out[0] & !H1_out[1]);

--F1L6 is com_digit:54|Decoder~60
--operation mode is normal

F1L6 = H1_out[2] & (!H1_out[0] & !H1_out[1]);


--F1L2 is com_digit:54|Decoder~56
--operation mode is normal

F1L2 = H1_out[1] & H1_out[0] & (!H1_out[2]);

--F1L7 is com_digit:54|Decoder~61
--operation mode is normal

F1L7 = H1_out[1] & H1_out[0] & (!H1_out[2]);


--F1L3 is com_digit:54|Decoder~57
--operation mode is normal

F1L3 = H1_out[1] & (!H1_out[2] & !H1_out[0]);

--F1L8 is com_digit:54|Decoder~62
--operation mode is normal

F1L8 = H1_out[1] & (!H1_out[2] & !H1_out[0]);


--F1L4 is com_digit:54|Decoder~58
--operation mode is normal

F1L4 = H1_out[0] & (!H1_out[1] & !H1_out[2]);

--F1L9 is com_digit:54|Decoder~63
--operation mode is normal

F1L9 = H1_out[0] & (!H1_out[1] & !H1_out[2]);


--F1L5 is com_digit:54|Decoder~59
--operation mode is normal

F1L5 = !H1_out[1] & !H1_out[2] & !H1_out[0];

--F1L01 is com_digit:54|Decoder~64
--operation mode is normal

F1L01 = !H1_out[1] & !H1_out[2] & !H1_out[0];


--G1_q[1] is key_scan:inst|q[1]
--operation mode is normal

G1_q[1]_lut_out = G1_q[1] $ G1_q[0];
G1_q[1] = DFFEA(G1_q[1]_lut_out, J1_clk_scan, , , G1L31, , );

--G1L41Q is key_scan:inst|q[1]~19
--operation mode is normal

G1L41Q = G1_q[1];


--G1_q[0] is key_scan:inst|q[0]
--operation mode is normal

G1_q[0]_lut_out = !G1_q[0];
G1_q[0] = DFFEA(G1_q[0]_lut_out, J1_clk_scan, , , G1L31, , );

--G1L11Q is key_scan:inst|q[0]~20
--operation mode is normal

G1L11Q = G1_q[0];


--G1L1 is key_scan:inst|Decoder~26
--operation mode is normal

G1L1 = G1_q[1] & G1_q[0];

--G1L5 is key_scan:inst|Decoder~30
--operation mode is normal

G1L5 = G1_q[1] & G1_q[0];


--G1L2 is key_scan:inst|Decoder~27
--operation mode is normal

G1L2 = G1_q[1] & (!G1_q[0]);

--G1L6 is key_scan:inst|Decoder~31
--operation mode is normal

G1L6 = G1_q[1] & (!G1_q[0]);


--G1L3 is key_scan:inst|Decoder~28
--operation mode is normal

G1L3 = G1_q[0] & (!G1_q[1]);

--G1L7 is key_scan:inst|Decoder~32
--operation mode is normal

G1L7 = G1_q[0] & (!G1_q[1]);


--G1L4 is key_scan:inst|Decoder~29
--operation mode is normal

G1L4 = G1_q[1] # G1_q[0];

--G1L8 is key_scan:inst|Decoder~33
--operation mode is normal

G1L8 = G1_q[1] # G1_q[0];


--D1_out2[0] is mux1_6:49|out2[0]
--operation mode is normal

D1_out2[0]_lut_out = D1_out1[0];
D1_out2[0] = DFFEA(D1_out2[0]_lut_out, !G1L52, , , , , );

--D1L12Q is mux1_6:49|out2[0]~4
--operation mode is normal

D1L12Q = D1_out2[0];


--D1_out1[0] is mux1_6:49|out1[0]
--operation mode is normal

D1_out1[0]_lut_out = D1_out0[0];
D1_out1[0] = DFFEA(D1_out1[0]_lut_out, !G1L52, , , , , );

--D1L21Q is mux1_6:49|out1[0]~4
--operation mode is normal

D1L21Q = D1_out1[0];


--D1_out0[0] is mux1_6:49|out0[0]
--operation mode is normal

D1_out0[0]_lut_out = G1_qout[0];
D1_out0[0] = DFFEA(D1_out0[0]_lut_out, !G1L52, , , , , );

--D1L3Q is mux1_6:49|out0[0]~4
--operation mode is normal

D1L3Q = D1_out0[0];


--E1L1 is mux6_1:53|qout[0]~360
--operation mode is normal

E1L1 = H1_out[1] & (H1_out[0]) # !H1_out[1] & (H1_out[0] & D1_out1[0] # !H1_out[0] & (D1_out0[0]));

--E1L5 is mux6_1:53|qout[0]~376
--operation mode is normal

E1L5 = H1_out[1] & (H1_out[0]) # !H1_out[1] & (H1_out[0] & D1_out1[0] # !H1_out[0] & (D1_out0[0]));


--D1_out3[0] is mux1_6:49|out3[0]
--operation mode is normal

D1_out3[0]_lut_out = D1_out2[0];
D1_out3[0] = DFFEA(D1_out3[0]_lut_out, !G1L52, , , , , );

--D1L03Q is mux1_6:49|out3[0]~4
--operation mode is normal

D1L03Q = D1_out3[0];


--E1L2 is mux6_1:53|qout[0]~361
--operation mode is normal

E1L2 = H1_out[1] & (E1L1 & (D1_out3[0]) # !E1L1 & D1_out2[0]) # !H1_out[1] & (E1L1);

--E1L6 is mux6_1:53|qout[0]~377
--operation mode is normal

E1L6 = H1_out[1] & (E1L1 & (D1_out3[0]) # !E1L1 & D1_out2[0]) # !H1_out[1] & (E1L1);


--D1_out5[0] is mux1_6:49|out5[0]
--operation mode is normal

D1_out5[0]_lut_out = D1_out4[0];
D1_out5[0] = DFFEA(D1_out5[0]_lut_out, !G1L52, , , , , );

--D1L84Q is mux1_6:49|out5[0]~4
--operation mode is normal

D1L84Q = D1_out5[0];


--D1_out4[0] is mux1_6:49|out4[0]
--operation mode is normal

D1_out4[0]_lut_out = D1_out3[0];
D1_out4[0] = DFFEA(D1_out4[0]_lut_out, !G1L52, , , , , );

--D1L93Q is mux1_6:49|out4[0]~4
--operation mode is normal

D1L93Q = D1_out4[0];


--E1L3 is mux6_1:53|qout[0]~362
--operation mode is normal

E1L3 = H1_out[0] & D1_out5[0] # !H1_out[0] & (D1_out4[0]);

--E1L7 is mux6_1:53|qout[0]~378
--operation mode is normal

E1L7 = H1_out[0] & D1_out5[0] # !H1_out[0] & (D1_out4[0]);


--E1L4 is mux6_1:53|qout[0]~363
--operation mode is normal

E1L4 = H1_out[2] & (E1L3 & !H1_out[1]) # !H1_out[2] & E1L2;

--E1L8 is mux6_1:53|qout[0]~379
--operation mode is normal

E1L8 = H1_out[2] & (E1L3 & !H1_out[1]) # !H1_out[2] & E1L2;


--D1_out2[1] is mux1_6:49|out2[1]
--operation mode is normal

D1_out2[1]_lut_out = D1_out1[1];
D1_out2[1] = DFFEA(D1_out2[1]_lut_out, !G1L52, , , , , );

--D1L32Q is mux1_6:49|out2[1]~5
--operation mode is normal

D1L32Q = D1_out2[1];


--D1_out1[1] is mux1_6:49|out1[1]
--operation mode is normal

D1_out1[1]_lut_out = D1_out0[1];
D1_out1[1] = DFFEA(D1_out1[1]_lut_out, !G1L52, , , , , );

--D1L41Q is mux1_6:49|out1[1]~5
--operation mode is normal

D1L41Q = D1_out1[1];


--D1_out0[1] is mux1_6:49|out0[1]
--operation mode is normal

D1_out0[1]_lut_out = G1_qout[1];
D1_out0[1] = DFFEA(D1_out0[1]_lut_out, !G1L52, , , , , );

--D1L5Q is mux1_6:49|out0[1]~5
--operation mode is normal

D1L5Q = D1_out0[1];


--E1L9 is mux6_1:53|qout[1]~364
--operation mode is normal

E1L9 = H1_out[1] & (H1_out[0]) # !H1_out[1] & (H1_out[0] & D1_out1[1] # !H1_out[0] & (D1_out0[1]));

--E1L31 is mux6_1:53|qout[1]~380
--operation mode is normal

E1L31 = H1_out[1] & (H1_out[0]) # !H1_out[1] & (H1_out[0] & D1_out1[1] # !H1_out[0] & (D1_out0[1]));


--D1_out3[1] is mux1_6:49|out3[1]
--operation mode is normal

D1_out3[1]_lut_out = D1_out2[1];
D1_out3[1] = DFFEA(D1_out3[1]_lut_out, !G1L52, , , , , );

--D1L23Q is mux1_6:49|out3[1]~5
--operation mode is normal

D1L23Q = D1_out3[1];


--E1L01 is mux6_1:53|qout[1]~365
--operation mode is normal

E1L01 = H1_out[1] & (E1L9 & (D1_out3[1]) # !E1L9 & D1_out2[1]) # !H1_out[1] & (E1L9);

--E1L41 is mux6_1:53|qout[1]~381
--operation mode is normal

E1L41 = H1_out[1] & (E1L9 & (D1_out3[1]) # !E1L9 & D1_out2[1]) # !H1_out[1] & (E1L9);


--D1_out5[1] is mux1_6:49|out5[1]
--operation mode is normal

D1_out5[1]_lut_out = D1_out4[1];
D1_out5[1] = DFFEA(D1_out5[1]_lut_out, !G1L52, , , , , );

--D1L05Q is mux1_6:49|out5[1]~5
--operation mode is normal

D1L05Q = D1_out5[1];


--D1_out4[1] is mux1_6:49|out4[1]
--operation mode is normal

D1_out4[1]_lut_out = D1_out3[1];
D1_out4[1] = DFFEA(D1_out4[1]_lut_out, !G1L52, , , , , );

--D1L14Q is mux1_6:49|out4[1]~5
--operation mode is normal

D1L14Q = D1_out4[1];


--E1L11 is mux6_1:53|qout[1]~366
--operation mode is normal

E1L11 = H1_out[0] & D1_out5[1] # !H1_out[0] & (D1_out4[1]);

--E1L51 is mux6_1:53|qout[1]~382
--operation mode is normal

E1L51 = H1_out[0] & D1_out5[1] # !H1_out[0] & (D1_out4[1]);


--E1L21 is mux6_1:53|qout[1]~367
--operation mode is normal

E1L21 = H1_out[2] & (E1L11 & !H1_out[1]) # !H1_out[2] & E1L01;

--E1L61 is mux6_1:53|qout[1]~383
--operation mode is normal

E1L61 = H1_out[2] & (E1L11 & !H1_out[1]) # !H1_out[2] & E1L01;


--D1_out1[2] is mux1_6:49|out1[2]
--operation mode is normal

D1_out1[2]_lut_out = D1_out0[2];
D1_out1[2] = DFFEA(D1_out1[2]_lut_out, !G1L52, , , , , );

--D1L61Q is mux1_6:49|out1[2]~6
--operation mode is normal

D1L61Q = D1_out1[2];


--D1_out2[2] is mux1_6:49|out2[2]
--operation mode is normal

D1_out2[2]_lut_out = D1_out1[2];
D1_out2[2] = DFFEA(D1_out2[2]_lut_out, !G1L52, , , , , );

--D1L52Q is mux1_6:49|out2[2]~6
--operation mode is normal

D1L52Q = D1_out2[2];


--D1_out0[2] is mux1_6:49|out0[2]
--operation mode is normal

D1_out0[2]_lut_out = G1_qout[2];
D1_out0[2] = DFFEA(D1_out0[2]_lut_out, !G1L52, , , , , );

--D1L7Q is mux1_6:49|out0[2]~6
--operation mode is normal

D1L7Q = D1_out0[2];


--E1L71 is mux6_1:53|qout[2]~368
--operation mode is normal

E1L71 = H1_out[0] & (H1_out[1]) # !H1_out[0] & (H1_out[1] & D1_out2[2] # !H1_out[1] & (D1_out0[2]));

--E1L12 is mux6_1:53|qout[2]~384
--operation mode is normal

E1L12 = H1_out[0] & (H1_out[1]) # !H1_out[0] & (H1_out[1] & D1_out2[2] # !H1_out[1] & (D1_out0[2]));


--D1_out3[2] is mux1_6:49|out3[2]
--operation mode is normal

D1_out3[2]_lut_out = D1_out2[2];
D1_out3[2] = DFFEA(D1_out3[2]_lut_out, !G1L52, , , , , );

--D1L43Q is mux1_6:49|out3[2]~6
--operation mode is normal

D1L43Q = D1_out3[2];


--E1L81 is mux6_1:53|qout[2]~369
--operation mode is normal

E1L81 = H1_out[0] & (E1L71 & (D1_out3[2]) # !E1L71 & D1_out1[2]) # !H1_out[0] & (E1L71);

--E1L22 is mux6_1:53|qout[2]~385
--operation mode is normal

E1L22 = H1_out[0] & (E1L71 & (D1_out3[2]) # !E1L71 & D1_out1[2]) # !H1_out[0] & (E1L71);


--D1_out5[2] is mux1_6:49|out5[2]
--operation mode is normal

D1_out5[2]_lut_out = D1_out4[2];
D1_out5[2] = DFFEA(D1_out5[2]_lut_out, !G1L52, , , , , );

--D1L25Q is mux1_6:49|out5[2]~6
--operation mode is normal

D1L25Q = D1_out5[2];


--D1_out4[2] is mux1_6:49|out4[2]
--operation mode is normal

D1_out4[2]_lut_out = D1_out3[2];
D1_out4[2] = DFFEA(D1_out4[2]_lut_out, !G1L52, , , , , );

--D1L34Q is mux1_6:49|out4[2]~6
--operation mode is normal

D1L34Q = D1_out4[2];


--E1L91 is mux6_1:53|qout[2]~370
--operation mode is normal

E1L91 = H1_out[0] & D1_out5[2] # !H1_out[0] & (D1_out4[2]);

--E1L32 is mux6_1:53|qout[2]~386
--operation mode is normal

E1L32 = H1_out[0] & D1_out5[2] # !H1_out[0] & (D1_out4[2]);