key_scan1.map.rpt

用verilog实现的四乘四键盘程序,在Quartus II上编译通过并成功

; OPTIMIZE_FOR_SPEED     ; 1           ; Untyped                                       ;
; USE_CS_BUFFERS         ; 1           ; Untyped                                       ;
; CARRY_CHAIN            ; MANUAL      ; Untyped                                       ;
; CARRY_CHAIN_LENGTH     ; 48          ; CARRY_CHAIN_LENGTH                            ;
; DEVICE_FAMILY          ; ACEX1K      ; Untyped                                       ;
; USE_WYS                ; OFF         ; Untyped                                       ;
; STYLE                  ; FAST        ; Untyped                                       ;
; CBXI_PARAMETER         ; add_sub_5nh ; Untyped                                       ;
; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                                    ;
; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                                  ;
; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                                  ;
; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                                ;
+------------------------+-------------+-----------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: div_clk:inst3|lpm_add_sub:add_rtl_1 ;
+------------------------+-------------+-----------------------------------------------+
; Parameter Name         ; Value       ; Type                                          ;
+------------------------+-------------+-----------------------------------------------+
; LPM_WIDTH              ; 32          ; Untyped                                       ;
; LPM_REPRESENTATION     ; UNSIGNED    ; Untyped                                       ;
; LPM_DIRECTION          ; ADD         ; Untyped                                       ;
; ONE_INPUT_IS_CONSTANT  ; YES         ; Untyped                                       ;
; LPM_PIPELINE           ; 0           ; Untyped                                       ;
; MAXIMIZE_SPEED         ; 5           ; Untyped                                       ;
; REGISTERED_AT_END      ; 0           ; Untyped                                       ;
; OPTIMIZE_FOR_SPEED     ; 1           ; Untyped                                       ;
; USE_CS_BUFFERS         ; 1           ; Untyped                                       ;
; CARRY_CHAIN            ; MANUAL      ; Untyped                                       ;
; CARRY_CHAIN_LENGTH     ; 48          ; CARRY_CHAIN_LENGTH                            ;
; DEVICE_FAMILY          ; ACEX1K      ; Untyped                                       ;
; USE_WYS                ; OFF         ; Untyped                                       ;
; STYLE                  ; FAST        ; Untyped                                       ;
; CBXI_PARAMETER         ; add_sub_5nh ; Untyped                                       ;
; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                                    ;
; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                                  ;
; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                                  ;
; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                                ;
+------------------------+-------------+-----------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in F:/verilog/jingshai/key_scan1/key_scan1.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
    Info: Processing started: Mon Sep 05 19:26:11 2005
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off key_scan1 -c key_scan1
Info: Found 1 design units, including 1 entities, in source file com_digit.v
    Info: Found entity 1: com_digit
Info: Found 1 design units, including 1 entities, in source file cout6.v
    Info: Found entity 1: cout6
Info: Found 1 design units, including 1 entities, in source file d.v
    Info: Found entity 1: d
Info: Found 1 design units, including 1 entities, in source file decode47.v
    Info: Found entity 1: decode47
Info: Found 1 design units, including 1 entities, in source file div_clk.v
    Info: Found entity 1: div_clk
Info: Found 1 design units, including 1 entities, in source file key_scan.v
    Info: Found entity 1: key_scan
Info: Found 1 design units, including 1 entities, in source file mux1_6.v
    Info: Found entity 1: mux1_6
Info: Found 1 design units, including 1 entities, in source file mux6_1.v
    Info: Found entity 1: mux6_1
Info: Found 1 design units, including 1 entities, in source file key_scan1.bdf
    Info: Found entity 1: key_scan1
Info: Elaborating entity "key_scan1" for the top level hierarchy
Warning: Block or symbol "mux6_1" of instance "53" overlaps another block or symbol
Warning: Port "rst" of type mux1_6 and instance "49" is missing source signal
Warning: Port "clk" of type mux1_6 and instance "49" is missing source signal
Info: Elaborating entity "com_digit" for hierarchy "com_digit:54"
Info: Elaborating entity "cout6" for hierarchy "cout6:inst2"
Warning: Verilog HDL assignment warning at cout6.v(11): truncated value with size 32 to match size of target (3)
Info: Elaborating entity "div_clk" for hierarchy "div_clk:inst3"
Info: (10035) Verilog HDL or VHDL information at div_clk.v(9): object "clk_qudou" declared but not used
Info: (10035) Verilog HDL or VHDL information at div_clk.v(11): object "j" declared but not used
Info: Elaborating entity "key_scan" for hierarchy "key_scan:inst"
Warning: Verilog HDL assignment warning at key_scan.v(45): truncated value with size 32 to match size of target (2)
Warning: Verilog HDL Always Construct warning at key_scan.v(65): variable "retn_in0" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning: Verilog HDL Always Construct warning at key_scan.v(65): variable "retn_in1" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning: Verilog HDL Always Construct warning at key_scan.v(65): variable "retn_in2" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning: Verilog HDL Always Construct warning at key_scan.v(65): variable "retn_in3" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning: Verilog HDL Always Construct warning at key_scan.v(65): variable "qout" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning: Verilog HDL assignment warning at key_scan.v(65): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at key_scan.v(66): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL Always Construct warning at key_scan.v(63): variable "qout" may not be assigned a new value in every possible path through the Always Construct.  Variable "qout" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Info: Using design file qudou.gdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: qudou
Info: Elaborating entity "qudou" for hierarchy "qudou:6"
Info: Elaborating entity "d" for hierarchy "qudou:6|d:17"
Info: Elaborating entity "decode47" for hierarchy "decode47:37"
Info: Elaborating entity "mux6_1" for hierarchy "mux6_1:53"
Info: Elaborating entity "mux1_6" for hierarchy "mux1_6:49"
Info: Found 1 design units, including 1 entities, in source file d:/altera/quar5.0/libraries/megafunctions/lpm_add_sub.tdf
    Info: Found entity 1: lpm_add_sub
Info: Found 1 design units, including 1 entities, in source file d:/altera/quar5.0/libraries/megafunctions/addcore.tdf
    Info: Found entity 1: addcore
Info: Found 1 design units, including 1 entities, in source file d:/altera/quar5.0/libraries/megafunctions/a_csnbuffer.tdf
    Info: Found entity 1: a_csnbuffer
Info: Found 1 design units, including 1 entities, in source file d:/altera/quar5.0/libraries/megafunctions/altshift.tdf
    Info: Found entity 1: altshift
Info: Registers with preset signals will power-up high
Info: Implemented 254 device resources after synthesis - the final resource count might be different
    Info: Implemented 6 input pins
    Info: Implemented 17 output pins
    Info: Implemented 231 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 13 warnings
    Info: Processing ended: Mon Sep 05 19:26:16 2005
    Info: Elapsed time: 00:00:05