div_clk.v

来自「用verilog实现的四乘四键盘程序,在Quartus II上编译通过并成功」· Verilog 代码 · 共 26 行

module div_clk(clk_200hz,clk_scan,clk_in,rst);

output clk_scan,clk_200hz;
reg    clk_scan,clk_200hz;

input  clk_in;
input  rst;

reg    clk_qudou;

integer i,j,k;

always @(posedge clk_200hz or negedge rst)
  begin
    if(~rst)        k=1;
    else if(k==4)   begin clk_scan=~clk_scan;k=1;end
    else             k=k+1;
  end

always @(posedge  clk_in)
  begin
    if(i==20000)   begin clk_200hz=~clk_200hz;i=1;end
    else                 i=i+1;
  end

endmodule