📄 mux1_6.rpt
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_LC6_B11 = LCELL( _EQ014);
_EQ014 = !int0 & in3 & _LC2_A4
# int0 & _LC2_B11
# !_LC2_A4 & _LC2_B11;
-- Node name is ':247'
-- Equation name is '_LC4_B11', type is buried
_LC4_B11 = LCELL( _EQ015);
_EQ015 = !int0 & in2 & _LC2_A4
# int0 & _LC8_B11
# !_LC2_A4 & _LC8_B11;
-- Node name is ':248'
-- Equation name is '_LC3_B11', type is buried
_LC3_B11 = LCELL( _EQ016);
_EQ016 = !int0 & in1 & _LC2_A4
# int0 & _LC7_B11
# !_LC2_A4 & _LC7_B11;
-- Node name is ':249'
-- Equation name is '_LC6_A15', type is buried
_LC6_A15 = LCELL( _EQ017);
_EQ017 = !int0 & in0 & _LC2_A4
# int0 & _LC7_A15
# !_LC2_A4 & _LC7_A15;
-- Node name is ':251'
-- Equation name is '_LC2_B11', type is buried
_LC2_B11 = DFFE( _LC6_B11, GLOBAL( clk), VCC, VCC, rst);
-- Node name is ':252'
-- Equation name is '_LC8_B11', type is buried
_LC8_B11 = DFFE( _LC4_B11, GLOBAL( clk), VCC, VCC, rst);
-- Node name is ':253'
-- Equation name is '_LC7_B11', type is buried
_LC7_B11 = DFFE( _LC3_B11, GLOBAL( clk), VCC, VCC, rst);
-- Node name is ':254'
-- Equation name is '_LC7_A15', type is buried
_LC7_A15 = DFFE( _LC6_A15, GLOBAL( clk), VCC, VCC, rst);
-- Node name is ':281'
-- Equation name is '_LC7_A1', type is buried
_LC7_A1 = LCELL( _EQ018);
_EQ018 = !int0 & in3 & _LC3_A4
# _LC1_A1 & !_LC3_A4
# int0 & _LC1_A1;
-- Node name is ':282'
-- Equation name is '_LC5_A15', type is buried
_LC5_A15 = LCELL( _EQ019);
_EQ019 = !int0 & in2 & _LC3_A4
# !_LC3_A4 & _LC3_A15
# int0 & _LC3_A15;
-- Node name is ':283'
-- Equation name is '_LC4_A15', type is buried
_LC4_A15 = LCELL( _EQ020);
_EQ020 = !int0 & in1 & _LC3_A4
# _LC1_A15 & !_LC3_A4
# int0 & _LC1_A15;
-- Node name is ':284'
-- Equation name is '_LC2_A15', type is buried
_LC2_A15 = LCELL( _EQ021);
_EQ021 = !int0 & in0 & _LC3_A4
# !_LC3_A4 & _LC8_A15
# int0 & _LC8_A15;
-- Node name is ':286'
-- Equation name is '_LC1_A1', type is buried
_LC1_A1 = DFFE( _LC7_A1, GLOBAL( clk), VCC, VCC, rst);
-- Node name is ':287'
-- Equation name is '_LC3_A15', type is buried
_LC3_A15 = DFFE( _LC5_A15, GLOBAL( clk), VCC, VCC, rst);
-- Node name is ':288'
-- Equation name is '_LC1_A15', type is buried
_LC1_A15 = DFFE( _LC4_A15, GLOBAL( clk), VCC, VCC, rst);
-- Node name is ':289'
-- Equation name is '_LC8_A15', type is buried
_LC8_A15 = DFFE( _LC2_A15, GLOBAL( clk), VCC, VCC, rst);
-- Node name is ':316'
-- Equation name is '_LC6_A1', type is buried
_LC6_A1 = LCELL( _EQ022);
_EQ022 = !int0 & in3 & _LC1_A4
# !_LC1_A4 & _LC3_A1
# int0 & _LC3_A1;
-- Node name is ':317'
-- Equation name is '_LC8_C12', type is buried
_LC8_C12 = LCELL( _EQ023);
_EQ023 = !int0 & in2 & _LC1_A4
# !_LC1_A4 & _LC6_C12
# int0 & _LC6_C12;
-- Node name is ':318'
-- Equation name is '_LC7_C12', type is buried
_LC7_C12 = LCELL( _EQ024);
_EQ024 = !int0 & in1 & _LC1_A4
# !_LC1_A4 & _LC3_C12
# int0 & _LC3_C12;
-- Node name is ':319'
-- Equation name is '_LC4_C12', type is buried
_LC4_C12 = LCELL( _EQ025);
_EQ025 = !int0 & in0 & _LC1_A4
# !_LC1_A4 & _LC5_C12
# int0 & _LC5_C12;
-- Node name is ':321'
-- Equation name is '_LC3_A1', type is buried
_LC3_A1 = DFFE( _LC6_A1, GLOBAL( clk), VCC, VCC, rst);
-- Node name is ':322'
-- Equation name is '_LC6_C12', type is buried
_LC6_C12 = DFFE( _LC8_C12, GLOBAL( clk), VCC, VCC, rst);
-- Node name is ':323'
-- Equation name is '_LC3_C12', type is buried
_LC3_C12 = DFFE( _LC7_C12, GLOBAL( clk), VCC, VCC, rst);
-- Node name is ':324'
-- Equation name is '_LC5_C12', type is buried
_LC5_C12 = DFFE( _LC4_C12, GLOBAL( clk), VCC, VCC, rst);
-- Node name is ':351'
-- Equation name is '_LC5_A1', type is buried
_LC5_A1 = LCELL( _EQ026);
_EQ026 = !int0 & in3 & _LC4_A4
# int0 & _LC2_A1
# _LC2_A1 & !_LC4_A4;
-- Node name is ':352'
-- Equation name is '_LC3_A8', type is buried
_LC3_A8 = LCELL( _EQ027);
_EQ027 = !int0 & in2 & _LC4_A4
# int0 & _LC1_A8
# _LC1_A8 & !_LC4_A4;
-- Node name is ':353'
-- Equation name is '_LC1_B11', type is buried
_LC1_B11 = LCELL( _EQ028);
_EQ028 = !int0 & in1 & _LC4_A4
# int0 & _LC5_B11
# !_LC4_A4 & _LC5_B11;
-- Node name is ':354'
-- Equation name is '_LC2_C12', type is buried
_LC2_C12 = LCELL( _EQ029);
_EQ029 = !int0 & in0 & _LC4_A4
# int0 & _LC1_C12
# _LC1_C12 & !_LC4_A4;
-- Node name is ':356'
-- Equation name is '_LC2_A1', type is buried
_LC2_A1 = DFFE( _LC5_A1, GLOBAL( clk), VCC, VCC, rst);
-- Node name is ':357'
-- Equation name is '_LC1_A8', type is buried
_LC1_A8 = DFFE( _LC3_A8, GLOBAL( clk), VCC, VCC, rst);
-- Node name is ':358'
-- Equation name is '_LC5_B11', type is buried
_LC5_B11 = DFFE( _LC1_B11, GLOBAL( clk), VCC, VCC, rst);
-- Node name is ':359'
-- Equation name is '_LC1_C12', type is buried
_LC1_C12 = DFFE( _LC2_C12, GLOBAL( clk), VCC, VCC, rst);
-- Node name is ':386'
-- Equation name is '_LC8_B7', type is buried
_LC8_B7 = LCELL( _EQ030);
_EQ030 = !int0 & in3 & _LC7_A4
# _LC4_B7 & !_LC7_A4
# int0 & _LC4_B7;
-- Node name is ':387'
-- Equation name is '_LC7_B7', type is buried
_LC7_B7 = LCELL( _EQ031);
_EQ031 = !int0 & in2 & _LC7_A4
# _LC6_B7 & !_LC7_A4
# int0 & _LC6_B7;
-- Node name is ':388'
-- Equation name is '_LC5_B7', type is buried
_LC5_B7 = LCELL( _EQ032);
_EQ032 = !int0 & in1 & _LC7_A4
# _LC3_B7 & !_LC7_A4
# int0 & _LC3_B7;
-- Node name is ':389'
-- Equation name is '_LC2_B7', type is buried
_LC2_B7 = LCELL( _EQ033);
_EQ033 = !int0 & in0 & _LC7_A4
# _LC1_B7 & !_LC7_A4
# int0 & _LC1_B7;
-- Node name is ':391'
-- Equation name is '_LC4_B7', type is buried
_LC4_B7 = DFFE( _LC8_B7, GLOBAL( clk), VCC, VCC, rst);
-- Node name is ':392'
-- Equation name is '_LC6_B7', type is buried
_LC6_B7 = DFFE( _LC7_B7, GLOBAL( clk), VCC, VCC, rst);
-- Node name is ':393'
-- Equation name is '_LC3_B7', type is buried
_LC3_B7 = DFFE( _LC5_B7, GLOBAL( clk), VCC, VCC, rst);
-- Node name is ':394'
-- Equation name is '_LC1_B7', type is buried
_LC1_B7 = DFFE( _LC2_B7, GLOBAL( clk), VCC, VCC, rst);
Project Information f:\verilog\竞赛\key_scan1\mux1_6.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'ACEX1K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:01
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 84,689K
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