📄 mux1_6.rpt
字号:
- 1 - A 01 DFFE + 1 1 1 1 :286
- 3 - A 15 DFFE + 1 1 1 1 :287
- 1 - A 15 DFFE + 1 1 1 1 :288
- 8 - A 15 DFFE + 1 1 1 1 :289
- 6 - A 01 OR2 2 2 0 1 :316
- 8 - C 12 OR2 2 2 0 1 :317
- 7 - C 12 OR2 2 2 0 1 :318
- 4 - C 12 OR2 2 2 0 1 :319
- 3 - A 01 DFFE + 1 1 1 1 :321
- 6 - C 12 DFFE + 1 1 1 1 :322
- 3 - C 12 DFFE + 1 1 1 1 :323
- 5 - C 12 DFFE + 1 1 1 1 :324
- 5 - A 01 OR2 2 2 0 1 :351
- 3 - A 08 OR2 2 2 0 1 :352
- 1 - B 11 OR2 2 2 0 1 :353
- 2 - C 12 OR2 2 2 0 1 :354
- 2 - A 01 DFFE + 1 1 1 1 :356
- 1 - A 08 DFFE + 1 1 1 1 :357
- 5 - B 11 DFFE + 1 1 1 1 :358
- 1 - C 12 DFFE + 1 1 1 1 :359
- 8 - B 07 OR2 2 2 0 1 :386
- 7 - B 07 OR2 2 2 0 1 :387
- 5 - B 07 OR2 2 2 0 1 :388
- 2 - B 07 OR2 2 2 0 1 :389
- 4 - B 07 DFFE + 1 1 1 1 :391
- 6 - B 07 DFFE + 1 1 1 1 :392
- 3 - B 07 DFFE + 1 1 1 1 :393
- 1 - B 07 DFFE + 1 1 1 1 :394
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: f:\verilog\竞赛\key_scan1\mux1_6.rpt
mux1_6
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 10/ 96( 10%) 4/ 48( 8%) 2/ 48( 4%) 0/16( 0%) 9/16( 56%) 0/16( 0%)
B: 7/ 96( 7%) 5/ 48( 10%) 0/ 48( 0%) 0/16( 0%) 8/16( 50%) 0/16( 0%)
C: 2/ 96( 2%) 4/ 48( 8%) 0/ 48( 0%) 0/16( 0%) 4/16( 25%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
03: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 3/24( 12%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
09: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: f:\verilog\竞赛\key_scan1\mux1_6.rpt
mux1_6
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 27 clk
Device-Specific Information: f:\verilog\竞赛\key_scan1\mux1_6.rpt
mux1_6
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 27 rst
Device-Specific Information: f:\verilog\竞赛\key_scan1\mux1_6.rpt
mux1_6
** EQUATIONS **
clk : INPUT;
int0 : INPUT;
in0 : INPUT;
in1 : INPUT;
in2 : INPUT;
in3 : INPUT;
rst : INPUT;
-- Node name is 'out00'
-- Equation name is 'out00', type is output
out00 = _LC6_A8;
-- Node name is 'out01'
-- Equation name is 'out01', type is output
out01 = _LC5_A8;
-- Node name is 'out02'
-- Equation name is 'out02', type is output
out02 = _LC2_A8;
-- Node name is 'out03'
-- Equation name is 'out03', type is output
out03 = _LC4_A1;
-- Node name is 'out10'
-- Equation name is 'out10', type is output
out10 = _LC7_A15;
-- Node name is 'out11'
-- Equation name is 'out11', type is output
out11 = _LC7_B11;
-- Node name is 'out12'
-- Equation name is 'out12', type is output
out12 = _LC8_B11;
-- Node name is 'out13'
-- Equation name is 'out13', type is output
out13 = _LC2_B11;
-- Node name is 'out20'
-- Equation name is 'out20', type is output
out20 = _LC8_A15;
-- Node name is 'out21'
-- Equation name is 'out21', type is output
out21 = _LC1_A15;
-- Node name is 'out22'
-- Equation name is 'out22', type is output
out22 = _LC3_A15;
-- Node name is 'out23'
-- Equation name is 'out23', type is output
out23 = _LC1_A1;
-- Node name is 'out30'
-- Equation name is 'out30', type is output
out30 = _LC5_C12;
-- Node name is 'out31'
-- Equation name is 'out31', type is output
out31 = _LC3_C12;
-- Node name is 'out32'
-- Equation name is 'out32', type is output
out32 = _LC6_C12;
-- Node name is 'out33'
-- Equation name is 'out33', type is output
out33 = _LC3_A1;
-- Node name is 'out40'
-- Equation name is 'out40', type is output
out40 = _LC1_C12;
-- Node name is 'out41'
-- Equation name is 'out41', type is output
out41 = _LC5_B11;
-- Node name is 'out42'
-- Equation name is 'out42', type is output
out42 = _LC1_A8;
-- Node name is 'out43'
-- Equation name is 'out43', type is output
out43 = _LC2_A1;
-- Node name is 'out50'
-- Equation name is 'out50', type is output
out50 = _LC1_B7;
-- Node name is 'out51'
-- Equation name is 'out51', type is output
out51 = _LC3_B7;
-- Node name is 'out52'
-- Equation name is 'out52', type is output
out52 = _LC6_B7;
-- Node name is 'out53'
-- Equation name is 'out53', type is output
out53 = _LC4_B7;
-- Node name is ':188' = 'state0'
-- Equation name is 'state0', location is LC2_A9, type is buried.
state0 = DFFE( _EQ001, GLOBAL( clk), GLOBAL( rst), VCC, VCC);
_EQ001 = !int0 & !state0;
-- Node name is ':187' = 'state1'
-- Equation name is 'state1', location is LC6_A4, type is buried.
state1 = DFFE( _EQ002, GLOBAL( clk), GLOBAL( rst), VCC, VCC);
_EQ002 = !int0 & _LC4_A4
# !int0 & _LC5_A4
# !int0 & _LC2_A4;
-- Node name is ':186' = 'state2'
-- Equation name is 'state2', location is LC8_A4, type is buried.
state2 = DFFE( _EQ003, GLOBAL( clk), GLOBAL( rst), VCC, VCC);
_EQ003 = !int0 & _LC3_A4
# !int0 & _LC1_A4
# !int0 & _LC4_A4;
-- Node name is ':52'
-- Equation name is '_LC5_A4', type is buried
_LC5_A4 = LCELL( _EQ004);
_EQ004 = state0 & !state1 & !state2;
-- Node name is ':72'
-- Equation name is '_LC2_A4', type is buried
_LC2_A4 = LCELL( _EQ005);
_EQ005 = !state0 & state1 & !state2;
-- Node name is ':92'
-- Equation name is '_LC3_A4', type is buried
_LC3_A4 = LCELL( _EQ006);
_EQ006 = state0 & state1 & !state2;
-- Node name is ':112'
-- Equation name is '_LC1_A4', type is buried
_LC1_A4 = LCELL( _EQ007);
_EQ007 = !state0 & !state1 & state2;
-- Node name is ':132'
-- Equation name is '_LC4_A4', type is buried
_LC4_A4 = LCELL( _EQ008);
_EQ008 = state0 & !state1 & state2;
-- Node name is ':152'
-- Equation name is '_LC7_A4', type is buried
!_LC7_A4 = _LC7_A4~NOT;
_LC7_A4~NOT = LCELL( _EQ009);
_EQ009 = !state1
# state0
# !state2;
-- Node name is ':211'
-- Equation name is '_LC8_A1', type is buried
_LC8_A1 = LCELL( _EQ010);
_EQ010 = !int0 & in3 & _LC5_A4
# int0 & _LC4_A1
# _LC4_A1 & !_LC5_A4;
-- Node name is ':212'
-- Equation name is '_LC8_A8', type is buried
_LC8_A8 = LCELL( _EQ011);
_EQ011 = !int0 & in2 & _LC5_A4
# int0 & _LC2_A8
# _LC2_A8 & !_LC5_A4;
-- Node name is ':213'
-- Equation name is '_LC7_A8', type is buried
_LC7_A8 = LCELL( _EQ012);
_EQ012 = !int0 & in1 & _LC5_A4
# int0 & _LC5_A8
# !_LC5_A4 & _LC5_A8;
-- Node name is ':214'
-- Equation name is '_LC4_A8', type is buried
_LC4_A8 = LCELL( _EQ013);
_EQ013 = !int0 & in0 & _LC5_A4
# int0 & _LC6_A8
# !_LC5_A4 & _LC6_A8;
-- Node name is ':216'
-- Equation name is '_LC4_A1', type is buried
_LC4_A1 = DFFE( _LC8_A1, GLOBAL( clk), VCC, VCC, rst);
-- Node name is ':217'
-- Equation name is '_LC2_A8', type is buried
_LC2_A8 = DFFE( _LC8_A8, GLOBAL( clk), VCC, VCC, rst);
-- Node name is ':218'
-- Equation name is '_LC5_A8', type is buried
_LC5_A8 = DFFE( _LC7_A8, GLOBAL( clk), VCC, VCC, rst);
-- Node name is ':219'
-- Equation name is '_LC6_A8', type is buried
_LC6_A8 = DFFE( _LC4_A8, GLOBAL( clk), VCC, VCC, rst);
-- Node name is ':246'
-- Equation name is '_LC6_B11', type is buried
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