key_scan1.fit.summary

用verilog实现的四乘四键盘程序,在Quartus II上编译通过并成功

Flow Status : Successful - Mon Sep 05 19:26:28 2005
Quartus II Version : 5.0 Build 148 04/26/2005 SJ Full Version
Revision Name : key_scan1
Top-level Entity Name : key_scan1
Family : ACEX1K
Device : EP1K30QC208-3
Timing Models : Final
Met timing requirements : N/A
Total logic elements : 231 / 1,728 ( 13 % )
Total pins : 23 / 147 ( 15 % )
Total memory bits : 0 / 24,576 ( 0 % )
Total PLLs : 0