mux1_6.v

用verilog实现的四乘四键盘程序,在Quartus II上编译通过并成功

module mux1_6(out0,out1,out2,out3,out4,out5,in,int0);
 
output[3:0] out0,out1,out2,out3,out4,out5;
reg[3:0]    out0,out1,out2,out3,out4,out5;

input       int0;
input[3:0]  in;

//reg[2:0]    state;

always @(posedge int0)
  begin    
     out5<=out4;
     out4<=out3;
     out3<=out2;
     out2<=out1;   
     out1<=out0; 
     out0<=in;   
  end
    
/*parameter q1=3'b000,
          q2=3'b001,
          q3=3'b011,
          q4=3'b100,
          q5=3'b101,
          q6=3'b110;

always @(negedge int0 or negedge rst )
  begin
   if(~rst)
     state=q1;     
   else 
    begin
     case(state)       
        q1:
           begin
             out0=in;
             state=q2;
           end

        q2:
           begin
             out1=in;
             state=q3;
           end
	      
        q3:
           begin
              state=q4;
              out2=in;
           end
	      
        q4:
           begin
              out3=in;
              state=q5;
           end
	     
        q5:
           begin
              out4=in;
              state=q6;           
           end
	        
        q6:        
           begin
               out5=in;
               state=q1;              
           end

           default: state=q1;
        endcase
     end     
   end
 */        

endmodule