key_scan1.v

用verilog实现的四乘四键盘程序,在Quartus II上编译通过并成功

module key_scan1(scan_out,qout,retn_in0,retn_in1,retn_in2,retn_in3,clk_scan,int);

//output[1:0] retn_out;
/*output[7:0]    bit;
 reg[7:0]       bit;
*/

output[3:0]    qout;
output[3:0] scan_out;
output         int;
reg            int;
//output[1:0] q;
input       retn_in0,retn_in1,retn_in2,retn_in3;
reg[1:0]    retn_out;
reg[3:0]    scan_out;
input       clk_scan;
wire[1:0]   scan_in;
reg[3:0]    qout;
reg[1:0]    q;


/*always @(posedge clk_scan)
   bit<=8'b11111111;
*/

always @(posedge clk_scan)
  begin
    if({retn_in0,retn_in1,retn_in2,retn_in3}==4'b1111)  retn_out=retn_out;
    else
      begin
        if(retn_in0==1'b0)  retn_out=2'b00;
        else if(retn_in1==1'b0) retn_out=2'b01;
        else if(retn_in2==1'b0) retn_out=2'b10;
        else if(retn_in3==1'b0) retn_out=2'b11;
      end
   end

  always @(posedge clk_scan)
    begin  
      if({retn_in0,retn_in1,retn_in2,retn_in3}==4'b1111) 
         begin  if(q==2'b11)  q=2'b00;
                else          q=q+1;
         end
      else                   q=q;       
    end

 assign scan_in=q;
  
  always @(scan_in)
    begin
      case(scan_in)
      2'b00:  scan_out=4'b1110;
      2'b01:  scan_out=4'b1101;
      2'b10:  scan_out=4'b1011;
      2'b11:  scan_out=4'b0111;
      endcase
    end


 always @(q or retn_out)
    begin
      if({retn_in0,retn_in1,retn_in2,retn_in3}==4'b1111)  begin qout=qout;int=1; end
      else    begin  qout={q,retn_out};int=0; end
    end
  
  
endmodule