📄 key_scan2.rpt
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52: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: f:\verilog\竞赛\key_scan1\key_scan2.rpt
key_scan2
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 44 clk_in
DFF 32 |div_clk:42|:143
Device-Specific Information: f:\verilog\竞赛\key_scan1\key_scan2.rpt
key_scan2
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 63 rst
Device-Specific Information: f:\verilog\竞赛\key_scan1\key_scan2.rpt
key_scan2
** EQUATIONS **
clk_in : INPUT;
diny1 : INPUT;
diny2 : INPUT;
diny3 : INPUT;
diny4 : INPUT;
rst : INPUT;
-- Node name is 'com_dec_bit0'
-- Equation name is 'com_dec_bit0', type is output
com_dec_bit0 = _LC4_K23;
-- Node name is 'com_dec_bit1'
-- Equation name is 'com_dec_bit1', type is output
com_dec_bit1 = _LC1_K23;
-- Node name is 'com_dec_bit2'
-- Equation name is 'com_dec_bit2', type is output
com_dec_bit2 = _LC2_K22;
-- Node name is 'com_dec_bit3'
-- Equation name is 'com_dec_bit3', type is output
com_dec_bit3 = _LC1_K22;
-- Node name is 'com_dec_bit4'
-- Equation name is 'com_dec_bit4', type is output
com_dec_bit4 = _LC4_K22;
-- Node name is 'com_dec_bit5'
-- Equation name is 'com_dec_bit5', type is output
com_dec_bit5 = _LC7_K19;
-- Node name is 'scan_out0'
-- Equation name is 'scan_out0', type is output
scan_out0 = _LC1_K10;
-- Node name is 'scan_out1'
-- Equation name is 'scan_out1', type is output
scan_out1 = _LC6_K10;
-- Node name is 'scan_out2'
-- Equation name is 'scan_out2', type is output
scan_out2 = _LC4_K10;
-- Node name is 'scan_out3'
-- Equation name is 'scan_out3', type is output
scan_out3 = _LC2_K10;
-- Node name is 'segment0'
-- Equation name is 'segment0', type is output
segment0 = _LC2_E28;
-- Node name is 'segment1'
-- Equation name is 'segment1', type is output
segment1 = _LC1_E30;
-- Node name is 'segment2'
-- Equation name is 'segment2', type is output
segment2 = _LC4_E34;
-- Node name is 'segment3'
-- Equation name is 'segment3', type is output
segment3 = _LC2_E36;
-- Node name is 'segment4'
-- Equation name is 'segment4', type is output
segment4 = _LC8_E38;
-- Node name is 'segment5'
-- Equation name is 'segment5', type is output
segment5 = _LC4_E38;
-- Node name is 'segment6'
-- Equation name is 'segment6', type is output
segment6 = _LC4_E40;
-- Node name is '|cout6:61|:13'
-- Equation name is '_LC7_K19', type is buried
!_LC7_K19 = _LC7_K19~NOT;
_LC7_K19~NOT = LCELL( _EQ001);
_EQ001 = !_LC5_K19
# !_LC4_K19
# _LC3_K19;
-- Node name is '|cout6:61|:33'
-- Equation name is '_LC5_K19', type is buried
_LC5_K19 = DFFE( _EQ002, GLOBAL( clk_in), VCC, VCC, VCC);
_EQ002 = !_LC4_K19 & _LC5_K19 & rst
# _LC3_K19 & _LC4_K19 & !_LC5_K19 & rst;
-- Node name is '|cout6:61|:34'
-- Equation name is '_LC3_K19', type is buried
_LC3_K19 = DFFE( _EQ003, GLOBAL( clk_in), VCC, VCC, VCC);
_EQ003 = !_LC3_K19 & _LC4_K19 & !_LC7_K19 & rst
# _LC3_K19 & !_LC4_K19 & !_LC7_K19 & rst;
-- Node name is '|cout6:61|:35'
-- Equation name is '_LC4_K19', type is buried
_LC4_K19 = DFFE( _EQ004, GLOBAL( clk_in), VCC, VCC, VCC);
_EQ004 = !_LC4_K19 & rst;
-- Node name is '|decode47:37|:12'
-- Equation name is '_LC1_E38', type is buried
_LC1_E38 = LCELL( _EQ005);
_EQ005 = !_LC1_K48 & !_LC1_K52 & !_LC6_K39 & !_LC7_K43;
-- Node name is '|decode47:37|:36'
-- Equation name is '_LC6_E38', type is buried
_LC6_E38 = LCELL( _EQ006);
_EQ006 = !_LC1_K48 & !_LC1_K52 & !_LC6_K39 & _LC7_K43;
-- Node name is '|decode47:37|:48'
-- Equation name is '_LC2_E38', type is buried
_LC2_E38 = LCELL( _EQ007);
_EQ007 = !_LC1_K48 & !_LC1_K52 & _LC6_K39 & _LC7_K43;
-- Node name is '|decode47:37|:149'
-- Equation name is '_LC4_E40', type is buried
_LC4_E40 = LCELL( _EQ008);
_EQ008 = !_LC1_K48 & _LC1_K52 & _LC6_K39
# !_LC1_K48 & !_LC1_K52 & !_LC6_K39
# _LC1_K48 & !_LC1_K52 & !_LC7_K43
# !_LC1_K48 & _LC7_K43;
-- Node name is '|decode47:37|~150~1'
-- Equation name is '_LC5_E38', type is buried
-- synthesized logic cell
_LC5_E38 = LCELL( _EQ009);
_EQ009 = _LC1_K48 & !_LC1_K52 & !_LC7_K43
# !_LC1_K48 & _LC1_K52 & !_LC6_K39 & !_LC7_K43;
-- Node name is '|decode47:37|~150~2'
-- Equation name is '_LC7_E38', type is buried
-- synthesized logic cell
_LC7_E38 = LCELL( _EQ010);
_EQ010 = !_LC1_K48 & _LC6_K39 & _LC7_K43
# !_LC1_K48 & !_LC1_K52 & _LC6_K39;
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