cout6.rpt

用verilog实现的四乘四键盘程序,在Quartus II上编译通过并成功

16:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
17:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
18:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
19:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
20:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
21:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
22:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
23:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
24:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
25:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
26:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
27:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
28:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
29:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
30:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
31:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
32:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
33:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
34:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
35:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
36:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
37:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
38:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
39:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
40:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
41:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
42:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
43:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
44:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
45:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
46:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
47:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
48:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
49:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
50:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
51:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
52:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
EA:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)


Device-Specific Information:               f:\verilog\竞赛\key_scan1\cout6.rpt
cout6

** CLOCK SIGNALS **

Type     Fan-out       Name
INPUT        3         clk


Device-Specific Information:               f:\verilog\竞赛\key_scan1\cout6.rpt
cout6

** EQUATIONS **

clk      : INPUT;
rst      : INPUT;

-- Node name is 'out0' 
-- Equation name is 'out0', type is output 
out0     =  _LC4_B5;

-- Node name is 'out1' 
-- Equation name is 'out1', type is output 
out1     =  _LC8_B5;

-- Node name is 'out2' 
-- Equation name is 'out2', type is output 
out2     =  _LC6_B5;

-- Node name is ':33' 
-- Equation name is '_LC6_B5', type is buried 
_LC6_B5  = DFFE( _EQ001, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ001 =  _LC4_B5 & !_LC6_B5 &  _LC8_B5 &  rst
         # !_LC4_B5 &  _LC6_B5 &  rst;

-- Node name is ':34' 
-- Equation name is '_LC8_B5', type is buried 
_LC8_B5  = DFFE( _EQ002, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ002 = !_LC4_B5 &  _LC8_B5 &  rst
         #  _LC4_B5 & !_LC6_B5 & !_LC8_B5 &  rst;

-- Node name is ':35' 
-- Equation name is '_LC4_B5', type is buried 
_LC4_B5  = DFFE( _EQ003, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ003 = !_LC4_B5 &  rst;



Project Information                        f:\verilog\竞赛\key_scan1\cout6.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'ACEX1K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:01
   Fitter                                 00:00:03
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:01
   --------------------------             --------
   Total Time                             00:00:05


Memory Allocated
-----------------

Peak memory allocated during compilation  = 50,723K