📄 key_scan1.map.talkback.xml
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<!--
This XML file (created on Mon Sep 05 19:26:16 2005) contains limited information
from the compilation of logic designs using Quartus II software (BUT NOT THE
LOGIC DESIGN FILES) that will be transmitted to Altera Corporation through
operation of the "TalkBack" feature. To enable/disable this feature, run
qtb_install.exe located in your quartus/bin folder. For more information, go
to license.txt.
-->
<talkback>
<ver>5.0</ver>
<schema>quartus_version_5.0_build_148.xsd</schema><license>
<host_id>00e04c423b3f</host_id>
<nic_id>00e04c423b3f</nic_id>
<cdrive_id>148e5930</cdrive_id>
</license>
<tool>
<name>Quartus II</name>
<version>5.0</version>
<build>Build 148</build>
<module>quartus_map.exe</module>
<edition>Full Version</edition>
<compilation_end_time>Mon Sep 05 19:26:16 2005</compilation_end_time>
</tool>
<machine>
<os>Windows XP</os>
<cpu>
<proc_count>1</proc_count>
<cpu_freq units="MHz">2666</cpu_freq>
</cpu>
<ram units="MB">504</ram>
</machine>
<top_file>F:/verilog/jingshai/key_scan1/key_scan1</top_file>
<mep_data>
<command_line>quartus_map --read_settings_files=on --write_settings_files=off key_scan1 -c key_scan1</command_line>
</mep_data>
<software_data>
<smart_recompile>off</smart_recompile>
</software_data>
<messages>
<warning>Warning: Verilog HDL Always Construct warning at key_scan.v(63): variable "qout" may not be assigned a new value in every possible path through the Always Construct. Variable "qout" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.</warning>
<warning>Warning: Verilog HDL assignment warning at key_scan.v(66): truncated value with size 32 to match size of target (1)</warning>
<warning>Warning: Verilog HDL assignment warning at key_scan.v(65): truncated value with size 32 to match size of target (1)</warning>
<warning>Warning: Verilog HDL Always Construct warning at key_scan.v(65): variable "qout" is read inside the Always Construct but isn't in the Always Construct's Event Control</warning>
<warning>Warning: Verilog HDL Always Construct warning at key_scan.v(65): variable "retn_in3" is read inside the Always Construct but isn't in the Always Construct's Event Control</warning>
<info>Info: Quartus II Analysis & Synthesis was successful. 0 errors, 13 warnings</info>
<info>Info: Elapsed time: 00:00:05</info>
<info>Info: Processing ended: Mon Sep 05 19:26:16 2005</info>
<info>Info: Implemented 254 device resources after synthesis - the final resource count might be different</info>
<info>Info: Implemented 231 logic cells</info>
</messages>
<analysis___synthesis_settings>
<row>
<option>Device</option>
<setting>EP1K30QC208-3</setting>
</row>
<row>
<option>Top-level entity name</option>
<setting>key_scan1</setting>
<default_value>key_scan1</default_value>
</row>
<row>
<option>Family name</option>
<setting>ACEX1K</setting>
<default_value>Stratix</default_value>
</row>
<row>
<option>Use smart compilation</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Create Debugging Nodes for IP Cores</option>
<setting>off</setting>
<default_value>off</default_value>
</row>
<row>
<option>Preserve fewer node names</option>
<setting>On</setting>
<default_value>On</default_value>
</row>
<row>
<option>Disable OpenCore Plus hardware evaluation</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Verilog Version</option>
<setting>Verilog_2001</setting>
<default_value>Verilog_2001</default_value>
</row>
<row>
<option>VHDL Version</option>
<setting>VHDL93</setting>
<default_value>VHDL93</default_value>
</row>
<row>
<option>State Machine Processing</option>
<setting>Auto</setting>
<default_value>Auto</default_value>
</row>
<row>
<option>Extract Verilog State Machines</option>
<setting>On</setting>
<default_value>On</default_value>
</row>
<row>
<option>Extract VHDL State Machines</option>
<setting>On</setting>
<default_value>On</default_value>
</row>
<row>
<option>Add Pass-Through Logic to Inferred RAMs</option>
<setting>On</setting>
<default_value>On</default_value>
</row>
<row>
<option>NOT Gate Push-Back</option>
<setting>On</setting>
<default_value>On</default_value>
</row>
<row>
<option>Power-Up Don't Care</option>
<setting>On</setting>
<default_value>On</default_value>
</row>
<row>
<option>Remove Redundant Logic Cells</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Remove Duplicate Registers</option>
<setting>On</setting>
<default_value>On</default_value>
</row>
<row>
<option>Ignore CARRY Buffers</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Ignore CASCADE Buffers</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Ignore GLOBAL Buffers</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Ignore ROW GLOBAL Buffers</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Ignore LCELL Buffers</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Ignore SOFT Buffers</option>
<setting>On</setting>
<default_value>On</default_value>
</row>
<row>
<option>Limit AHDL Integers to 32 Bits</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Auto Implement in ROM</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Optimization Technique -- FLEX 10K/10KE/10KA/ACEX 1K</option>
<setting>Area</setting>
<default_value>Area</default_value>
</row>
<row>
<option>Carry Chain Length -- FLEX 10K</option>
<setting>32</setting>
<default_value>32</default_value>
</row>
<row>
<option>Cascade Chain Length</option>
<setting>2</setting>
<default_value>2</default_value>
</row>
<row>
<option>Auto Carry Chains</option>
<setting>On</setting>
<default_value>On</default_value>
</row>
<row>
<option>Auto Open-Drain Pins</option>
<setting>On</setting>
<default_value>On</default_value>
</row>
<row>
<option>Remove Duplicate Logic</option>
<setting>On</setting>
<default_value>On</default_value>
</row>
<row>
<option>Auto ROM Replacement</option>
<setting>On</setting>
<default_value>On</default_value>
</row>
<row>
<option>Auto RAM Replacement</option>
<setting>On</setting>
<default_value>On</default_value>
</row>
<row>
<option>Auto Clock Enable Replacement</option>
<setting>On</setting>
<default_value>On</default_value>
</row>
<row>
<option>Auto Resource Sharing</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Allow Any RAM Size For Recognition</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Allow Any ROM Size For Recognition</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Ignore translate_off and translate_on Synthesis Directives</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Show Parameter Settings Tables in Synthesis Report</option>
<setting>On</setting>
<default_value>On</default_value>
</row>
</analysis___synthesis_settings>
<general_register_statistics>
<row>
<statistic>Total registers</statistic>
<value>105</value>
</row>
<row>
<statistic>Number of registers using Synchronous Clear</statistic>
<value>0</value>
</row>
<row>
<statistic>Number of registers using Synchronous Load</statistic>
<value>0</value>
</row>
<row>
<statistic>Number of registers using Asynchronous Clear</statistic>
<value>32</value>
</row>
<row>
<statistic>Number of registers using Asynchronous Load</statistic>
<value>0</value>
</row>
<row>
<statistic>Number of registers using Clock Enable</statistic>
<value>6</value>
</row>
<row>
<statistic>Number of registers using Preset</statistic>
<value>0</value>
</row>
</general_register_statistics>
<compilation_summary>
<flow_status>Successful - Mon Sep 05 19:26:16 2005</flow_status>
<quartus_ii_version>5.0 Build 148 04/26/2005 SJ Full Version</quartus_ii_version>
<revision_name>key_scan1</revision_name>
<top_level_entity_name>key_scan1</top_level_entity_name>
<family>ACEX1K</family>
<device>EP1K30QC208-3</device>
<timing_models>Final</timing_models>
<met_timing_requirements>N/A</met_timing_requirements>
<total_logic_elements>231</total_logic_elements>
<total_pins>23</total_pins>
<total_memory_bits>0</total_memory_bits>
<total_plls>0</total_plls>
</compilation_summary>
<compile_id>7B1E480D</compile_id>
</talkback>
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