key_scan1.tan.talkback.xml

用verilog实现的四乘四键盘程序,在Quartus II上编译通过并成功

<!--
This XML file (created on Mon Sep 05 19:26:37 2005) contains limited information
from the compilation of logic designs using Quartus II software (BUT NOT THE
LOGIC DESIGN FILES) that will be transmitted to Altera Corporation through
operation of the "TalkBack" feature.  To enable/disable this feature, run
qtb_install.exe located in your quartus/bin folder.  For more information, go
to license.txt.
-->
<talkback>
<ver>5.0</ver>
<schema>quartus_version_5.0_build_148.xsd</schema><license>
	<host_id>00e04c423b3f</host_id>
	<nic_id>00e04c423b3f</nic_id>
	<cdrive_id>148e5930</cdrive_id>
</license>
<tool>
	<name>Quartus II</name>
	<version>5.0</version>
	<build>Build 148</build>
	<module>quartus_tan.exe</module>
	<edition>Full Version</edition>
	<compilation_end_time>Mon Sep 05 19:26:37 2005</compilation_end_time>
</tool>
<machine>
	<os>Windows XP</os>
	<cpu>
		<proc_count>1</proc_count>
		<cpu_freq units="MHz">2666</cpu_freq>
	</cpu>
	<ram units="MB">504</ram>
</machine>
<top_file>F:/verilog/jingshai/key_scan1/key_scan1</top_file>
<mep_data>
	<command_line>quartus_tan --read_settings_files=off --write_settings_files=off key_scan1 -c key_scan1</command_line>
</mep_data>
<software_data>
	<smart_recompile>off</smart_recompile>
</software_data>
<messages>
	<warning>Warning: Circuit may not operate. Detected 27 non-operational path(s) clocked by clock &quot;clk_in&quot; with clock skew larger than data delay. See Compilation Report for details.</warning>
	<warning>Warning: Found 12 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew</warning>
	<warning>Warning: Found pins functioning as undefined clocks and/or memory enables</warning>
	<warning>Warning: Timing Analysis found one or more latches implemented as combinational loops</warning>
	<warning>Warning: Node &quot;key_scan:inst|qout[3]&quot; is a latch</warning>
	<info>Info: Quartus II Timing Analyzer was successful. 0 errors, 8 warnings</info>
	<info>Info: Elapsed time: 00:00:02</info>
	<info>Info: Processing ended: Mon Sep 05 19:26:36 2005</info>
	<info>Info: th for register &quot;qudou:13|d:17|q&quot; (data pin = &quot;diny4&quot;, clock pin = &quot;clk_in&quot;) is 4.800 ns</info>
	<info>Info: - Shortest pin to register delay is 2.900 ns</info>
</messages>
<clock_settings_summary>
	<row>
		<clock_node_name>clk_in</clock_node_name>
		<type>User Pin</type>
		<fmax_requirement>NONE</fmax_requirement>
		<early_latency units="ns">0.000</early_latency>
		<late_latency units="ns">0.000</late_latency>
		<based_on>NONE</based_on>
		<multiply_base_fmax_by>N/A</multiply_base_fmax_by>
		<divide_base_fmax_by>N/A</divide_base_fmax_by>
		<offset>N/A</offset>
	</row>
</clock_settings_summary>
<performance>
	<nonclk>
		<type>Worst-case tsu</type>
		<slack>N/A</slack>
		<required>None</required>
		<actual>4.100 ns</actual>
	</nonclk>
	<nonclk>
		<type>Worst-case tco</type>
		<slack>N/A</slack>
		<required>None</required>
		<actual>32.300 ns</actual>
	</nonclk>
	<nonclk>
		<type>Worst-case th</type>
		<slack>N/A</slack>
		<required>None</required>
		<actual>4.800 ns</actual>
	</nonclk>
	<clk>
		<name>clk_in</name>
		<slack>N/A</slack>
		<required>None</required>
		<actual>74.63 MHz ( period = 13.400 ns )</actual>
	</clk>
</performance>
<compile_id>73C64670</compile_id>
</talkback>