key_scan1.fit.talkback.xml

用verilog实现的四乘四键盘程序,在Quartus II上编译通过并成功

		<i_o_standard>LVTTL/LVCMOS</i_o_standard>
	</row>
	<row>
		<name>com_dec_bit[3]</name>
		<pin__>192</pin__>
		<col.>24</col.>
		<i_o_register>no</i_o_register>
		<use_local_routing_output>no</use_local_routing_output>
		<power_up_high>no</power_up_high>
		<slow_slew_rate>no</slow_slew_rate>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<single_pin_oe>no</single_pin_oe>
		<single_pin_ce>no</single_pin_ce>
		<open_drain>no</open_drain>
		<tri_primitive>no</tri_primitive>
		<i_o_standard>LVTTL/LVCMOS</i_o_standard>
	</row>
	<row>
		<name>com_dec_bit[2]</name>
		<pin__>193</pin__>
		<col.>25</col.>
		<i_o_register>no</i_o_register>
		<use_local_routing_output>no</use_local_routing_output>
		<power_up_high>no</power_up_high>
		<slow_slew_rate>no</slow_slew_rate>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<single_pin_oe>no</single_pin_oe>
		<single_pin_ce>no</single_pin_ce>
		<open_drain>no</open_drain>
		<tri_primitive>no</tri_primitive>
		<i_o_standard>LVTTL/LVCMOS</i_o_standard>
	</row>
	<row>
		<name>com_dec_bit[1]</name>
		<pin__>195</pin__>
		<col.>26</col.>
		<i_o_register>no</i_o_register>
		<use_local_routing_output>no</use_local_routing_output>
		<power_up_high>no</power_up_high>
		<slow_slew_rate>no</slow_slew_rate>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<single_pin_oe>no</single_pin_oe>
		<single_pin_ce>no</single_pin_ce>
		<open_drain>no</open_drain>
		<tri_primitive>no</tri_primitive>
		<i_o_standard>LVTTL/LVCMOS</i_o_standard>
	</row>
	<row>
		<name>com_dec_bit[0]</name>
		<pin__>196</pin__>
		<col.>27</col.>
		<i_o_register>no</i_o_register>
		<use_local_routing_output>no</use_local_routing_output>
		<power_up_high>no</power_up_high>
		<slow_slew_rate>no</slow_slew_rate>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<single_pin_oe>no</single_pin_oe>
		<single_pin_ce>no</single_pin_ce>
		<open_drain>no</open_drain>
		<tri_primitive>no</tri_primitive>
		<i_o_standard>LVTTL/LVCMOS</i_o_standard>
	</row>
	<row>
		<name>scan_out[3]</name>
		<pin__>87</pin__>
		<col.>14</col.>
		<i_o_register>no</i_o_register>
		<use_local_routing_output>no</use_local_routing_output>
		<power_up_high>no</power_up_high>
		<slow_slew_rate>no</slow_slew_rate>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<single_pin_oe>no</single_pin_oe>
		<single_pin_ce>no</single_pin_ce>
		<open_drain>no</open_drain>
		<tri_primitive>no</tri_primitive>
		<i_o_standard>LVTTL/LVCMOS</i_o_standard>
	</row>
	<row>
		<name>scan_out[2]</name>
		<pin__>86</pin__>
		<col.>15</col.>
		<i_o_register>no</i_o_register>
		<use_local_routing_output>no</use_local_routing_output>
		<power_up_high>no</power_up_high>
		<slow_slew_rate>no</slow_slew_rate>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<single_pin_oe>no</single_pin_oe>
		<single_pin_ce>no</single_pin_ce>
		<open_drain>no</open_drain>
		<tri_primitive>no</tri_primitive>
		<i_o_standard>LVTTL/LVCMOS</i_o_standard>
	</row>
	<row>
		<name>scan_out[1]</name>
		<pin__>85</pin__>
		<col.>16</col.>
		<i_o_register>no</i_o_register>
		<use_local_routing_output>no</use_local_routing_output>
		<power_up_high>no</power_up_high>
		<slow_slew_rate>no</slow_slew_rate>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<single_pin_oe>no</single_pin_oe>
		<single_pin_ce>no</single_pin_ce>
		<open_drain>no</open_drain>
		<tri_primitive>no</tri_primitive>
		<i_o_standard>LVTTL/LVCMOS</i_o_standard>
	</row>
	<row>
		<name>scan_out[0]</name>
		<pin__>83</pin__>
		<col.>17</col.>
		<i_o_register>no</i_o_register>
		<use_local_routing_output>no</use_local_routing_output>
		<power_up_high>no</power_up_high>
		<slow_slew_rate>no</slow_slew_rate>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<single_pin_oe>no</single_pin_oe>
		<single_pin_ce>no</single_pin_ce>
		<open_drain>no</open_drain>
		<tri_primitive>no</tri_primitive>
		<i_o_standard>LVTTL/LVCMOS</i_o_standard>
	</row>
	<row>
		<name>segment[6]</name>
		<pin__>199</pin__>
		<col.>29</col.>
		<i_o_register>no</i_o_register>
		<use_local_routing_output>no</use_local_routing_output>
		<power_up_high>no</power_up_high>
		<slow_slew_rate>no</slow_slew_rate>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<single_pin_oe>no</single_pin_oe>
		<single_pin_ce>no</single_pin_ce>
		<open_drain>no</open_drain>
		<tri_primitive>no</tri_primitive>
		<i_o_standard>LVTTL/LVCMOS</i_o_standard>
	</row>
	<row>
		<name>segment[5]</name>
		<pin__>200</pin__>
		<col.>30</col.>
		<i_o_register>no</i_o_register>
		<use_local_routing_output>no</use_local_routing_output>
		<power_up_high>no</power_up_high>
		<slow_slew_rate>no</slow_slew_rate>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<single_pin_oe>no</single_pin_oe>
		<single_pin_ce>no</single_pin_ce>
		<open_drain>no</open_drain>
		<tri_primitive>no</tri_primitive>
		<i_o_standard>LVTTL/LVCMOS</i_o_standard>
	</row>
	<row>
		<name>segment[4]</name>
		<pin__>202</pin__>
		<col.>31</col.>
		<i_o_register>no</i_o_register>
		<use_local_routing_output>no</use_local_routing_output>
		<power_up_high>no</power_up_high>
		<slow_slew_rate>no</slow_slew_rate>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<single_pin_oe>no</single_pin_oe>
		<single_pin_ce>no</single_pin_ce>
		<open_drain>no</open_drain>
		<tri_primitive>no</tri_primitive>
		<i_o_standard>LVTTL/LVCMOS</i_o_standard>
	</row>
	<row>
		<name>segment[3]</name>
		<pin__>203</pin__>
		<col.>32</col.>
		<i_o_register>no</i_o_register>
		<use_local_routing_output>no</use_local_routing_output>
		<power_up_high>no</power_up_high>
		<slow_slew_rate>no</slow_slew_rate>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<single_pin_oe>no</single_pin_oe>
		<single_pin_ce>no</single_pin_ce>
		<open_drain>no</open_drain>
		<tri_primitive>no</tri_primitive>
		<i_o_standard>LVTTL/LVCMOS</i_o_standard>
	</row>
	<row>
		<name>segment[2]</name>
		<pin__>204</pin__>
		<col.>33</col.>
		<i_o_register>no</i_o_register>
		<use_local_routing_output>no</use_local_routing_output>
		<power_up_high>no</power_up_high>
		<slow_slew_rate>no</slow_slew_rate>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<single_pin_oe>no</single_pin_oe>
		<single_pin_ce>no</single_pin_ce>
		<open_drain>no</open_drain>
		<tri_primitive>no</tri_primitive>
		<i_o_standard>LVTTL/LVCMOS</i_o_standard>
	</row>
	<row>
		<name>segment[1]</name>
		<pin__>205</pin__>
		<col.>34</col.>
		<i_o_register>no</i_o_register>
		<use_local_routing_output>no</use_local_routing_output>
		<power_up_high>no</power_up_high>
		<slow_slew_rate>no</slow_slew_rate>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<single_pin_oe>no</single_pin_oe>
		<single_pin_ce>no</single_pin_ce>
		<open_drain>no</open_drain>
		<tri_primitive>no</tri_primitive>
		<i_o_standard>LVTTL/LVCMOS</i_o_standard>
	</row>
	<row>
		<name>segment[0]</name>
		<pin__>206</pin__>
		<col.>34</col.>
		<i_o_register>no</i_o_register>
		<use_local_routing_output>no</use_local_routing_output>
		<power_up_high>no</power_up_high>
		<slow_slew_rate>no</slow_slew_rate>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<single_pin_oe>no</single_pin_oe>
		<single_pin_ce>no</single_pin_ce>
		<open_drain>no</open_drain>
		<tri_primitive>no</tri_primitive>
		<i_o_standard>LVTTL/LVCMOS</i_o_standard>
	</row>
</output_pins>
<compilation_summary>
	<flow_status>Successful - Mon Sep 05 19:26:28 2005</flow_status>
	<quartus_ii_version>5.0 Build 148 04/26/2005 SJ Full Version</quartus_ii_version>
	<revision_name>key_scan1</revision_name>
	<top_level_entity_name>key_scan1</top_level_entity_name>
	<family>ACEX1K</family>
	<device>EP1K30QC208-3</device>
	<timing_models>Final</timing_models>
	<met_timing_requirements>N/A</met_timing_requirements>
	<total_logic_elements>231 / 1,728 ( 13 % )</total_logic_elements>
	<total_pins>23 / 147 ( 15 % )</total_pins>
	<total_memory_bits>0 / 24,576 ( 0 % )</total_memory_bits>
	<total_plls>0</total_plls>
</compilation_summary>
<compile_id>D6923344</compile_id>
<files>
	<top>F:/verilog/jingshai/key_scan1/key_scan1.bdf</top>
	<extensions>
		<ext ext_name="v">8</ext>
		<ext ext_name="bdf">1</ext>
		<ext ext_name="gdf">1</ext>
		<ext ext_name="tdf">4</ext>
		<ext ext_name="inc">8</ext>
		<ext ext_name="lst">1</ext>
	</extensions>
	<sub_files>
		<sub_file>F:/verilog/jingshai/key_scan1/com_digit.v</sub_file>
		<sub_file>F:/verilog/jingshai/key_scan1/cout6.v</sub_file>
		<sub_file>F:/verilog/jingshai/key_scan1/d.v</sub_file>
		<sub_file>F:/verilog/jingshai/key_scan1/decode47.v</sub_file>
		<sub_file>F:/verilog/jingshai/key_scan1/div_clk.v</sub_file>
		<sub_file>F:/verilog/jingshai/key_scan1/key_scan.v</sub_file>
		<sub_file>F:/verilog/jingshai/key_scan1/mux1_6.v</sub_file>
		<sub_file>F:/verilog/jingshai/key_scan1/mux6_1.v</sub_file>
		<sub_file>F:/verilog/jingshai/key_scan1/key_scan1.bdf</sub_file>
		<sub_file>F:/verilog/jingshai/key_scan1/qudou.gdf</sub_file>
		<sub_file>d:/altera/quar5.0/libraries/megafunctions/lpm_add_sub.tdf</sub_file>
		<sub_file>d:/altera/quar5.0/libraries/megafunctions/addcore.inc</sub_file>
		<sub_file>d:/altera/quar5.0/libraries/megafunctions/look_add.inc</sub_file>
		<sub_file>d:/altera/quar5.0/libraries/megafunctions/bypassff.inc</sub_file>
		<sub_file>d:/altera/quar5.0/libraries/megafunctions/altshift.inc</sub_file>
		<sub_file>d:/altera/quar5.0/libraries/megafunctions/alt_stratix_add_sub.inc</sub_file>
		<sub_file>d:/altera/quar5.0/libraries/megafunctions/alt_mercury_add_sub.inc</sub_file>
		<sub_file>d:/altera/quar5.0/libraries/megafunctions/aglobal50.inc</sub_file>
		<sub_file>d:/altera/quar5.0/libraries/megafunctions/cbx.lst</sub_file>
		<sub_file>d:/altera/quar5.0/libraries/megafunctions/addcore.tdf</sub_file>
		<sub_file>d:/altera/quar5.0/libraries/megafunctions/a_csnbuffer.inc</sub_file>
		<sub_file>d:/altera/quar5.0/libraries/megafunctions/a_csnbuffer.tdf</sub_file>
		<sub_file>d:/altera/quar5.0/libraries/megafunctions/altshift.tdf</sub_file>
	</sub_files>
</files>
<architecture>
	<family>ACEX1K</family>
	<auto_device>OFF</auto_device>
	<device>EP1K30QC208-3</device>
</architecture>
<pkg_io>
	<pin_std count="23">LVTTL/LVCMOS</pin_std>
</pkg_io>
</talkback>