📄 unicntr.tan.rpt
字号:
; N/A ; None ; 4.200 ns ; mode[0] ; int_reg[4] ; clock ;
; N/A ; None ; 4.200 ns ; mode[0] ; int_reg[3] ; clock ;
; N/A ; None ; 4.200 ns ; mode[0] ; int_reg[2] ; clock ;
; N/A ; None ; 4.200 ns ; mode[0] ; int_reg[1] ; clock ;
; N/A ; None ; 4.200 ns ; mode[0] ; int_reg[7] ; clock ;
; N/A ; None ; 4.200 ns ; mode[1] ; int_reg[6] ; clock ;
; N/A ; None ; 4.200 ns ; mode[1] ; int_reg[5] ; clock ;
; N/A ; None ; 4.200 ns ; mode[1] ; int_reg[4] ; clock ;
; N/A ; None ; 4.200 ns ; mode[1] ; int_reg[3] ; clock ;
; N/A ; None ; 4.200 ns ; mode[1] ; int_reg[2] ; clock ;
; N/A ; None ; 4.200 ns ; mode[1] ; int_reg[1] ; clock ;
; N/A ; None ; 4.200 ns ; mode[1] ; int_reg[7] ; clock ;
; N/A ; None ; 3.300 ns ; serinr ; int_reg[7] ; clock ;
; N/A ; None ; 3.300 ns ; datain[0] ; int_reg[0] ; clock ;
; N/A ; None ; 3.300 ns ; serinl ; int_reg[0] ; clock ;
; N/A ; None ; 3.300 ns ; mode[2] ; int_reg[0] ; clock ;
; N/A ; None ; 3.300 ns ; mode[0] ; int_reg[0] ; clock ;
; N/A ; None ; 3.300 ns ; mode[1] ; int_reg[0] ; clock ;
+-------+--------------+------------+-----------+------------+----------+
+--------------------------------------------------------------------------+
; tco ;
+-------+--------------+------------+------------+------------+------------+
; Slack ; Required tco ; Actual tco ; From ; To ; From Clock ;
+-------+--------------+------------+------------+------------+------------+
; N/A ; None ; 7.400 ns ; int_reg[6] ; termcnt ; clock ;
; N/A ; None ; 7.400 ns ; int_reg[5] ; termcnt ; clock ;
; N/A ; None ; 7.400 ns ; int_reg[4] ; termcnt ; clock ;
; N/A ; None ; 7.400 ns ; int_reg[3] ; termcnt ; clock ;
; N/A ; None ; 7.400 ns ; int_reg[2] ; termcnt ; clock ;
; N/A ; None ; 7.400 ns ; int_reg[1] ; termcnt ; clock ;
; N/A ; None ; 7.400 ns ; int_reg[0] ; termcnt ; clock ;
; N/A ; None ; 7.400 ns ; int_reg[7] ; termcnt ; clock ;
; N/A ; None ; 2.800 ns ; int_reg[0] ; dataout[0] ; clock ;
; N/A ; None ; 2.800 ns ; int_reg[1] ; dataout[1] ; clock ;
; N/A ; None ; 2.800 ns ; int_reg[2] ; dataout[2] ; clock ;
; N/A ; None ; 2.800 ns ; int_reg[3] ; dataout[3] ; clock ;
; N/A ; None ; 2.800 ns ; int_reg[4] ; dataout[4] ; clock ;
; N/A ; None ; 2.800 ns ; int_reg[5] ; dataout[5] ; clock ;
; N/A ; None ; 2.800 ns ; int_reg[6] ; dataout[6] ; clock ;
; N/A ; None ; 2.800 ns ; int_reg[7] ; dataout[7] ; clock ;
+-------+--------------+------------+------------+------------+------------+
+-----------------------------------------------------------------------------+
; th ;
+---------------+-------------+-----------+-----------+------------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To ; To Clock ;
+---------------+-------------+-----------+-----------+------------+----------+
; N/A ; None ; -0.800 ns ; serinr ; int_reg[7] ; clock ;
; N/A ; None ; -0.800 ns ; datain[5] ; int_reg[5] ; clock ;
; N/A ; None ; -0.800 ns ; datain[4] ; int_reg[4] ; clock ;
; N/A ; None ; -0.800 ns ; datain[3] ; int_reg[3] ; clock ;
; N/A ; None ; -0.800 ns ; datain[0] ; int_reg[0] ; clock ;
; N/A ; None ; -0.800 ns ; serinl ; int_reg[0] ; clock ;
; N/A ; None ; -0.800 ns ; mode[2] ; int_reg[6] ; clock ;
; N/A ; None ; -0.800 ns ; mode[2] ; int_reg[5] ; clock ;
; N/A ; None ; -0.800 ns ; mode[2] ; int_reg[4] ; clock ;
; N/A ; None ; -0.800 ns ; mode[2] ; int_reg[3] ; clock ;
; N/A ; None ; -0.800 ns ; mode[2] ; int_reg[2] ; clock ;
; N/A ; None ; -0.800 ns ; mode[2] ; int_reg[1] ; clock ;
; N/A ; None ; -0.800 ns ; mode[2] ; int_reg[0] ; clock ;
; N/A ; None ; -0.800 ns ; mode[2] ; int_reg[7] ; clock ;
; N/A ; None ; -0.800 ns ; mode[0] ; int_reg[6] ; clock ;
; N/A ; None ; -0.800 ns ; mode[0] ; int_reg[5] ; clock ;
; N/A ; None ; -0.800 ns ; mode[0] ; int_reg[4] ; clock ;
; N/A ; None ; -0.800 ns ; mode[0] ; int_reg[3] ; clock ;
; N/A ; None ; -0.800 ns ; mode[0] ; int_reg[2] ; clock ;
; N/A ; None ; -0.800 ns ; mode[0] ; int_reg[1] ; clock ;
; N/A ; None ; -0.800 ns ; mode[0] ; int_reg[0] ; clock ;
; N/A ; None ; -0.800 ns ; mode[0] ; int_reg[7] ; clock ;
; N/A ; None ; -0.800 ns ; mode[1] ; int_reg[6] ; clock ;
; N/A ; None ; -0.800 ns ; mode[1] ; int_reg[5] ; clock ;
; N/A ; None ; -0.800 ns ; mode[1] ; int_reg[4] ; clock ;
; N/A ; None ; -0.800 ns ; mode[1] ; int_reg[3] ; clock ;
; N/A ; None ; -0.800 ns ; mode[1] ; int_reg[2] ; clock ;
; N/A ; None ; -0.800 ns ; mode[1] ; int_reg[1] ; clock ;
; N/A ; None ; -0.800 ns ; mode[1] ; int_reg[0] ; clock ;
; N/A ; None ; -0.800 ns ; mode[1] ; int_reg[7] ; clock ;
; N/A ; None ; -1.700 ns ; datain[6] ; int_reg[6] ; clock ;
; N/A ; None ; -1.700 ns ; datain[7] ; int_reg[7] ; clock ;
; N/A ; None ; -1.700 ns ; datain[2] ; int_reg[2] ; clock ;
; N/A ; None ; -1.700 ns ; datain[1] ; int_reg[1] ; clock ;
+---------------+-------------+-----------+-----------+------------+----------+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
Info: Version 5.0 Build 148 04/26/2005 SJ Web Edition
Info: Processing started: Mon Mar 13 09:27:31 2006
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off unicntr -c unicntr
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
Info: Assuming node "clock" is an undefined clock
Info: Clock "clock" has Internal fmax of 113.64 MHz between source register "int_reg[6]" and destination register "int_reg[7]" (period= 8.8 ns)
Info: + Longest register to register delay is 6.700 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC14; Fanout = 16; REG Node = 'int_reg[6]'
Info: 2: + IC(1.000 ns) + CELL(3.100 ns) = 4.100 ns; Loc. = SEXP6; Fanout = 1; COMB Node = 'Mux~3041'
Info: 3: + IC(0.000 ns) + CELL(2.600 ns) = 6.700 ns; Loc. = LC16; Fanout = 10; REG Node = 'int_reg[7]'
Info: Total cell delay = 5.700 ns ( 85.07 % )
Info: Total interconnect delay = 1.000 ns ( 14.93 % )
Info: - Smallest clock skew is 0.000 ns
Info: + Shortest clock path from clock "clock" to destination register is 1.300 ns
Info: 1: + IC(0.000 ns) + CELL(1.200 ns) = 1.200 ns; Loc. = PIN_43; Fanout = 8; CLK Node = 'clock'
Info: 2: + IC(0.000 ns) + CELL(0.100 ns) = 1.300 ns; Loc. = LC16; Fanout = 10; REG Node = 'int_reg[7]'
Info: Total cell delay = 1.300 ns ( 100.00 % )
Info: - Longest clock path from clock "clock" to source register is 1.300 ns
Info: 1: + IC(0.000 ns) + CELL(1.200 ns) = 1.200 ns; Loc. = PIN_43; Fanout = 8; CLK Node = 'clock'
Info: 2: + IC(0.000 ns) + CELL(0.100 ns) = 1.300 ns; Loc. = LC14; Fanout = 16; REG Node = 'int_reg[6]'
Info: Total cell delay = 1.300 ns ( 100.00 % )
Info: + Micro clock to output delay of source is 1.300 ns
Info: + Micro setup delay of destination is 0.800 ns
Info: tsu for register "int_reg[6]" (data pin = "datain[6]", clock pin = "clock") is 4.200 ns
Info: + Longest pin to register delay is 4.700 ns
Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_24; Fanout = 1; PIN Node = 'datain[6]'
Info: 2: + IC(1.000 ns) + CELL(2.600 ns) = 3.800 ns; Loc. = LC13; Fanout = 1; COMB Node = 'Mux~3101'
Info: 3: + IC(0.000 ns) + CELL(0.900 ns) = 4.700 ns; Loc. = LC14; Fanout = 16; REG Node = 'int_reg[6]'
Info: Total cell delay = 3.700 ns ( 78.72 % )
Info: Total interconnect delay = 1.000 ns ( 21.28 % )
Info: + Micro setup delay of destination is 0.800 ns
Info: - Shortest clock path from clock "clock" to destination register is 1.300 ns
Info: 1: + IC(0.000 ns) + CELL(1.200 ns) = 1.200 ns; Loc. = PIN_43; Fanout = 8; CLK Node = 'clock'
Info: 2: + IC(0.000 ns) + CELL(0.100 ns) = 1.300 ns; Loc. = LC14; Fanout = 16; REG Node = 'int_reg[6]'
Info: Total cell delay = 1.300 ns ( 100.00 % )
Info: tco from clock "clock" to destination pin "termcnt" through register "int_reg[6]" is 7.400 ns
Info: + Longest clock path from clock "clock" to source register is 1.300 ns
Info: 1: + IC(0.000 ns) + CELL(1.200 ns) = 1.200 ns; Loc. = PIN_43; Fanout = 8; CLK Node = 'clock'
Info: 2: + IC(0.000 ns) + CELL(0.100 ns) = 1.300 ns; Loc. = LC14; Fanout = 16; REG Node = 'int_reg[6]'
Info: Total cell delay = 1.300 ns ( 100.00 % )
Info: + Micro clock to output delay of source is 1.300 ns
Info: + Longest register to pin delay is 4.800 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC14; Fanout = 16; REG Node = 'int_reg[6]'
Info: 2: + IC(1.000 ns) + CELL(3.600 ns) = 4.600 ns; Loc. = LC8; Fanout = 1; COMB Node = 'det_zero~18'
Info: 3: + IC(0.000 ns) + CELL(0.200 ns) = 4.800 ns; Loc. = PIN_12; Fanout = 0; PIN Node = 'termcnt'
Info: Total cell delay = 3.800 ns ( 79.17 % )
Info: Total interconnect delay = 1.000 ns ( 20.83 % )
Info: th for register "int_reg[7]" (data pin = "serinr", clock pin = "clock") is -0.800 ns
Info: + Longest clock path from clock "clock" to destination register is 1.300 ns
Info: 1: + IC(0.000 ns) + CELL(1.200 ns) = 1.200 ns; Loc. = PIN_43; Fanout = 8; CLK Node = 'clock'
Info: 2: + IC(0.000 ns) + CELL(0.100 ns) = 1.300 ns; Loc. = LC16; Fanout = 10; REG Node = 'int_reg[7]'
Info: Total cell delay = 1.300 ns ( 100.00 % )
Info: + Micro hold delay of destination is 1.700 ns
Info: - Shortest pin to register delay is 3.800 ns
Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_26; Fanout = 1; PIN Node = 'serinr'
Info: 2: + IC(1.000 ns) + CELL(2.600 ns) = 3.800 ns; Loc. = LC16; Fanout = 10; REG Node = 'int_reg[7]'
Info: Total cell delay = 2.800 ns ( 73.68 % )
Info: Total interconnect delay = 1.000 ns ( 26.32 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
Info: Processing ended: Mon Mar 13 09:27:34 2006
Info: Elapsed time: 00:00:05
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