unicntr.map.eqn

通用寄存器的部分代码 LIBRARY IEEE USE IEEE.STD_LOGIC_1164.ALL ENTITY traffic IS PORT(clk,sm,sb:IN bit

-- Copyright (C) 1991-2005 Altera Corporation
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-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.
--A1L43 is Mux~3040
A1L43 = EXP(int_reg[6] & int_reg[5] & int_reg[4] & int_reg[2] & int_reg[0]);


--A1L53 is Mux~3041
A1L53 = EXP(!int_reg[5] & !int_reg[4] & !int_reg[6] & !int_reg[0] & !int_reg[2]);


--int_reg[7] is int_reg[7]
int_reg[7]_p0_out = int_reg[7] & mode[1] & A1L53 & !int_reg[1];
int_reg[7]_p1_out = int_reg[7] & mode[1] & mode[2];
int_reg[7]_p2_out = !mode[1] & mode[2] & mode[0] & serinr;
int_reg[7]_p3_out = !mode[1] & mode[2] & !mode[0] & int_reg[6];
int_reg[7]_p4_out = int_reg[7] & mode[1] & !mode[0] & A1L43;
int_reg[7]_or_out = A1L83 # int_reg[7]_p0_out # int_reg[7]_p1_out # int_reg[7]_p2_out # int_reg[7]_p3_out # int_reg[7]_p4_out;
int_reg[7]_reg_input = int_reg[7]_or_out;
int_reg[7] = DFFE(int_reg[7]_reg_input, GLOBAL(clock), , , );


--A1L02 is det_zero~18
A1L02_p1_out = !int_reg[7] & !int_reg[3] & !int_reg[2] & !int_reg[0] & !int_reg[1] & !int_reg[6] & !int_reg[4] & !int_reg[5];
A1L02_or_out = A1L02_p1_out;
A1L02 = A1L02_or_out;


--A1L63 is Mux~3048
A1L63 = EXP(int_reg[5] & int_reg[4] & int_reg[2] & int_reg[0]);


--A1L73 is Mux~3049
A1L73 = EXP(!int_reg[5] & !int_reg[4] & !int_reg[0] & !int_reg[2]);


--int_reg[6] is int_reg[6]
int_reg[6]_p0_out = int_reg[6] & mode[1] & A1L73 & !int_reg[1];
int_reg[6]_p1_out = int_reg[6] & mode[1] & mode[2];
int_reg[6]_p2_out = !mode[1] & mode[2] & mode[0] & int_reg[7];
int_reg[6]_p3_out = !mode[1] & mode[2] & !mode[0] & int_reg[5];
int_reg[6]_p4_out = int_reg[6] & mode[1] & !mode[0] & A1L63;
int_reg[6]_or_out = A1L93 # int_reg[6]_p0_out # int_reg[6]_p1_out # int_reg[6]_p2_out # int_reg[6]_p3_out # int_reg[6]_p4_out;
int_reg[6]_reg_input = int_reg[6]_or_out;
int_reg[6] = DFFE(int_reg[6]_reg_input, GLOBAL(clock), , , );


--int_reg[5] is int_reg[5]
int_reg[5]_p0_out = mode[1] & !int_reg[4] & mode[0] & !mode[2] & !int_reg[3] & !int_reg[2] & !int_reg[0] & !int_reg[1];
int_reg[5]_p1_out = !mode[1] & !int_reg[4] & !mode[0] & int_reg[5];
int_reg[5]_p2_out = !mode[1] & !mode[0] & int_reg[5] & !mode[2];
int_reg[5]_p3_out = !mode[1] & mode[0] & int_reg[5] & mode[2] & !int_reg[6];
int_reg[5]_p4_out = !mode[1] & int_reg[5] & !mode[2] & !datain[5];
int_reg[5]_or_out = A1L04 # int_reg[5]_p0_out # int_reg[5]_p1_out # int_reg[5]_p2_out # int_reg[5]_p3_out # int_reg[5]_p4_out;
int_reg[5]_reg_input = int_reg[5]_or_out;
int_reg[5] = TFFE(int_reg[5]_reg_input, GLOBAL(clock), , , );


--int_reg[4] is int_reg[4]
int_reg[4]_p0_out = mode[1] & !int_reg[3] & mode[0] & !mode[2] & !int_reg[2] & !int_reg[0] & !int_reg[1];
int_reg[4]_p1_out = !mode[1] & !int_reg[3] & !mode[0] & int_reg[4];
int_reg[4]_p2_out = !mode[1] & !mode[0] & int_reg[4] & !mode[2];
int_reg[4]_p3_out = !mode[1] & mode[0] & int_reg[4] & mode[2] & !int_reg[5];
int_reg[4]_p4_out = !mode[1] & int_reg[4] & !mode[2] & !datain[4];
int_reg[4]_or_out = A1L14 # int_reg[4]_p0_out # int_reg[4]_p1_out # int_reg[4]_p2_out # int_reg[4]_p3_out # int_reg[4]_p4_out;
int_reg[4]_reg_input = int_reg[4]_or_out;
int_reg[4] = TFFE(int_reg[4]_reg_input, GLOBAL(clock), , , );


--int_reg[3] is int_reg[3]
int_reg[3]_p0_out = mode[1] & !int_reg[2] & mode[0] & !mode[2] & !int_reg[0] & !int_reg[1];
int_reg[3]_p1_out = !mode[1] & !int_reg[2] & !mode[0] & int_reg[3];
int_reg[3]_p2_out = !mode[1] & !mode[0] & int_reg[3] & !mode[2];
int_reg[3]_p3_out = !mode[1] & mode[0] & int_reg[3] & mode[2] & !int_reg[4];
int_reg[3]_p4_out = !mode[1] & int_reg[3] & !mode[2] & !datain[3];
int_reg[3]_or_out = A1L24 # int_reg[3]_p0_out # int_reg[3]_p1_out # int_reg[3]_p2_out # int_reg[3]_p3_out # int_reg[3]_p4_out;
int_reg[3]_reg_input = int_reg[3]_or_out;
int_reg[3] = TFFE(int_reg[3]_reg_input, GLOBAL(clock), , , );


--int_reg[2] is int_reg[2]
int_reg[2]_p0_out = !mode[1] & !mode[0] & int_reg[1] & mode[2];
int_reg[2]_p1_out = !int_reg[0] & !int_reg[2] & mode[1] & mode[0] & !int_reg[1] & !mode[2];
int_reg[2]_p2_out = int_reg[0] & int_reg[2] & mode[1] & mode[0];
int_reg[2]_p3_out = int_reg[2] & mode[1] & mode[2];
int_reg[2]_p4_out = !mode[1] & mode[0] & mode[2] & int_reg[3];
int_reg[2]_or_out = A1L34 # int_reg[2]_p0_out # int_reg[2]_p1_out # int_reg[2]_p2_out # int_reg[2]_p3_out # int_reg[2]_p4_out;
int_reg[2]_reg_input = int_reg[2]_or_out;
int_reg[2] = DFFE(int_reg[2]_reg_input, GLOBAL(clock), , , );


--int_reg[1] is int_reg[1]
int_reg[1]_p0_out = mode[2] & !mode[1] & int_reg[0] & !mode[0];
int_reg[1]_p1_out = !int_reg[1] & !mode[2] & mode[1] & !int_reg[0] & mode[0];
int_reg[1]_p2_out = int_reg[1] & mode[1] & int_reg[0] & mode[0];
int_reg[1]_p3_out = int_reg[1] & mode[2] & mode[1];
int_reg[1]_p4_out = mode[2] & !mode[1] & mode[0] & int_reg[2];
int_reg[1]_or_out = A1L44 # int_reg[1]_p0_out # int_reg[1]_p1_out # int_reg[1]_p2_out # int_reg[1]_p3_out # int_reg[1]_p4_out;
int_reg[1]_reg_input = int_reg[1]_or_out;
int_reg[1] = DFFE(int_reg[1]_reg_input, GLOBAL(clock), , , );


--int_reg[0] is int_reg[0]
int_reg[0]_p0_out = mode[1] & mode[2] & int_reg[0];
int_reg[0]_p1_out = serinl & !mode[0] & !mode[1] & mode[2];
int_reg[0]_p2_out = mode[0] & !mode[1] & !mode[2] & datain[0];
int_reg[0]_p3_out = mode[0] & !mode[1] & mode[2] & int_reg[1];
int_reg[0]_p4_out = mode[1] & !mode[2] & !int_reg[0];
int_reg[0]_or_out = int_reg[0]_p0_out # int_reg[0]_p1_out # int_reg[0]_p2_out # int_reg[0]_p3_out # int_reg[0]_p4_out;
int_reg[0]_reg_input = int_reg[0]_or_out;
int_reg[0] = DFFE(int_reg[0]_reg_input, GLOBAL(clock), , , );


--A1L83 is Mux~3095
A1L83_p0_out = int_reg[7] & mode[1] & int_reg[3] & mode[0];
A1L83_p1_out = int_reg[7] & mode[1] & !int_reg[3] & int_reg[1];
A1L83_p2_out = !int_reg[7] & mode[1] & int_reg[3] & int_reg[1] & int_reg[6] & !mode[0] & int_reg[5] & int_reg[4] & int_reg[2] & int_reg[0] & !mode[2];
A1L83_p3_out = !mode[1] & mode[0] & !mode[2] & datain[7];
A1L83_p4_out = !int_reg[7] & mode[1] & !int_reg[3] & !int_reg[1] & !int_reg[6] & mode[0] & !int_reg[5] & !int_reg[4] & !int_reg[2] & !int_reg[0] & !mode[2];
A1L83 = A1L83_p0_out # A1L83_p1_out # A1L83_p2_out # A1L83_p3_out # A1L83_p4_out;


--A1L93 is Mux~3101
A1L93_p0_out = int_reg[6] & mode[1] & int_reg[3] & mode[0];
A1L93_p1_out = int_reg[6] & mode[1] & !int_reg[3] & int_reg[1];
A1L93_p2_out = !int_reg[6] & mode[1] & int_reg[3] & int_reg[1] & int_reg[5] & !mode[0] & int_reg[4] & int_reg[2] & int_reg[0] & !mode[2];
A1L93_p3_out = !mode[1] & mode[0] & !mode[2] & datain[6];
A1L93_p4_out = !int_reg[6] & mode[1] & !int_reg[3] & !int_reg[1] & !int_reg[5] & mode[0] & !int_reg[4] & !int_reg[2] & !int_reg[0] & !mode[2];
A1L93 = A1L93_p0_out # A1L93_p1_out # A1L93_p2_out # A1L93_p3_out # A1L93_p4_out;


--A1L04 is Mux~3107
A1L04_p1_out = mode[1] & int_reg[4] & int_reg[3] & !mode[0] & !mode[2] & int_reg[2] & int_reg[0] & int_reg[1];
A1L04_p2_out = !mode[1] & mode[0] & !mode[2] & datain[5] & !int_reg[5];
A1L04_p3_out = !mode[1] & mode[0] & mode[2] & !int_reg[5] & int_reg[6];
A1L04_p4_out = !mode[1] & int_reg[4] & !mode[0] & mode[2] & !int_reg[5];
A1L04 = A1L04_p1_out # A1L04_p2_out # A1L04_p3_out # A1L04_p4_out;


--A1L14 is Mux~3112
A1L14_p1_out = mode[1] & int_reg[3] & int_reg[2] & !mode[0] & !mode[2] & int_reg[0] & int_reg[1];
A1L14_p2_out = !mode[1] & mode[0] & !mode[2] & datain[4] & !int_reg[4];
A1L14_p3_out = !mode[1] & mode[0] & mode[2] & !int_reg[4] & int_reg[5];
A1L14_p4_out = !mode[1] & int_reg[3] & !mode[0] & mode[2] & !int_reg[4];
A1L14 = A1L14_p1_out # A1L14_p2_out # A1L14_p3_out # A1L14_p4_out;


--A1L24 is Mux~3117
A1L24_p1_out = mode[1] & int_reg[2] & int_reg[0] & !mode[0] & !mode[2] & int_reg[1];
A1L24_p2_out = !mode[1] & mode[0] & !mode[2] & datain[3] & !int_reg[3];
A1L24_p3_out = !mode[1] & mode[0] & mode[2] & !int_reg[3] & int_reg[4];
A1L24_p4_out = !mode[1] & int_reg[2] & !mode[0] & mode[2] & !int_reg[3];
A1L24 = A1L24_p1_out # A1L24_p2_out # A1L24_p3_out # A1L24_p4_out;


--A1L34 is Mux~3122
A1L34_p1_out = int_reg[2] & mode[1] & !mode[0] & !int_reg[1];
A1L34_p2_out = int_reg[2] & mode[1] & int_reg[1] & !int_reg[0];
A1L34_p3_out = !int_reg[2] & mode[1] & !mode[0] & int_reg[1] & int_reg[0] & !mode[2];
A1L34_p4_out = !mode[1] & mode[0] & !mode[2] & datain[2];
A1L34 = A1L34_p1_out # A1L34_p2_out # A1L34_p3_out # A1L34_p4_out;


--A1L44 is Mux~3127
A1L44_p1_out = !int_reg[1] & !mode[2] & mode[1] & int_reg[0] & !mode[0];
A1L44_p2_out = int_reg[1] & mode[1] & !int_reg[0] & !mode[0];
A1L44_p3_out = !mode[2] & !mode[1] & mode[0] & datain[1];
A1L44 = A1L44_p1_out # A1L44_p2_out # A1L44_p3_out;


--clock is clock
--operation mode is input

clock = INPUT();


--serinl is serinl
--operation mode is input

serinl = INPUT();


--serinr is serinr
--operation mode is input

serinr = INPUT();


--mode[0] is mode[0]
--operation mode is input

mode[0] = INPUT();


--mode[1] is mode[1]
--operation mode is input

mode[1] = INPUT();


--mode[2] is mode[2]
--operation mode is input

mode[2] = INPUT();


--datain[0] is datain[0]
--operation mode is input

datain[0] = INPUT();


--datain[1] is datain[1]
--operation mode is input

datain[1] = INPUT();


--datain[2] is datain[2]
--operation mode is input

datain[2] = INPUT();


--datain[3] is datain[3]
--operation mode is input

datain[3] = INPUT();


--datain[4] is datain[4]
--operation mode is input

datain[4] = INPUT();


--datain[5] is datain[5]
--operation mode is input

datain[5] = INPUT();


--datain[6] is datain[6]
--operation mode is input

datain[6] = INPUT();


--datain[7] is datain[7]
--operation mode is input

datain[7] = INPUT();


--dataout[7] is dataout[7]
--operation mode is output

dataout[7] = OUTPUT(int_reg[7]);


--termcnt is termcnt
--operation mode is output

termcnt = OUTPUT(A1L02);


--dataout[6] is dataout[6]
--operation mode is output

dataout[6] = OUTPUT(int_reg[6]);


--dataout[5] is dataout[5]
--operation mode is output

dataout[5] = OUTPUT(int_reg[5]);


--dataout[4] is dataout[4]
--operation mode is output

dataout[4] = OUTPUT(int_reg[4]);


--dataout[3] is dataout[3]
--operation mode is output

dataout[3] = OUTPUT(int_reg[3]);


--dataout[2] is dataout[2]
--operation mode is output

dataout[2] = OUTPUT(int_reg[2]);


--dataout[1] is dataout[1]
--operation mode is output

dataout[1] = OUTPUT(int_reg[1]);


--dataout[0] is dataout[0]
--operation mode is output

dataout[0] = OUTPUT(int_reg[0]);