tiaoping.tan.rpt

条屏控制器的CPLD编程,主要完成移位寄存器、编码器和译码器的功能

Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "p1_3" is an undefined clock
    Info: Assuming node "wr" is an undefined clock
    Info: Assuming node "clk" is an undefined clock
Info: Clock "p1_3" has Internal fmax of 99.01 MHz between source register "lpm_counter:addr_count_rtl_2|dffs[0]" and destination register "lpm_counter:addr_count_rtl_2|dffs[3]" (period= 10.1 ns)
    Info: + Longest register to register delay is 5.600 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC58; Fanout = 6; REG Node = 'lpm_counter:addr_count_rtl_2|dffs[0]'
        Info: 2: + IC(2.400 ns) + CELL(3.200 ns) = 5.600 ns; Loc. = LC34; Fanout = 3; REG Node = 'lpm_counter:addr_count_rtl_2|dffs[3]'
        Info: Total cell delay = 3.200 ns ( 57.14 % )
        Info: Total interconnect delay = 2.400 ns ( 42.86 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "p1_3" to destination register is 6.300 ns
            Info: 1: + IC(0.000 ns) + CELL(1.400 ns) = 1.400 ns; Loc. = PIN_8; Fanout = 9; CLK Node = 'p1_3'
            Info: 2: + IC(2.400 ns) + CELL(2.500 ns) = 6.300 ns; Loc. = LC34; Fanout = 3; REG Node = 'lpm_counter:addr_count_rtl_2|dffs[3]'
            Info: Total cell delay = 3.900 ns ( 61.90 % )
            Info: Total interconnect delay = 2.400 ns ( 38.10 % )
        Info: - Longest clock path from clock "p1_3" to source register is 6.300 ns
            Info: 1: + IC(0.000 ns) + CELL(1.400 ns) = 1.400 ns; Loc. = PIN_8; Fanout = 9; CLK Node = 'p1_3'
            Info: 2: + IC(2.400 ns) + CELL(2.500 ns) = 6.300 ns; Loc. = LC58; Fanout = 6; REG Node = 'lpm_counter:addr_count_rtl_2|dffs[0]'
            Info: Total cell delay = 3.900 ns ( 61.90 % )
            Info: Total interconnect delay = 2.400 ns ( 38.10 % )
    Info: + Micro clock to output delay of source is 1.600 ns
    Info: + Micro setup delay of destination is 2.900 ns
Info: Clock "wr" has Internal fmax of 98.04 MHz between source register "flag_counter" and destination register "flag_counter" (period= 10.2 ns)
    Info: + Longest register to register delay is 5.700 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC2; Fanout = 39; REG Node = 'flag_counter'
        Info: 2: + IC(2.500 ns) + CELL(3.200 ns) = 5.700 ns; Loc. = LC2; Fanout = 39; REG Node = 'flag_counter'
        Info: Total cell delay = 3.200 ns ( 56.14 % )
        Info: Total interconnect delay = 2.500 ns ( 43.86 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "wr" to destination register is 6.500 ns
            Info: 1: + IC(0.000 ns) + CELL(1.400 ns) = 1.400 ns; Loc. = PIN_10; Fanout = 47; CLK Node = 'wr'
            Info: 2: + IC(2.600 ns) + CELL(2.500 ns) = 6.500 ns; Loc. = LC2; Fanout = 39; REG Node = 'flag_counter'
            Info: Total cell delay = 3.900 ns ( 60.00 % )
            Info: Total interconnect delay = 2.600 ns ( 40.00 % )
        Info: - Longest clock path from clock "wr" to source register is 6.500 ns
            Info: 1: + IC(0.000 ns) + CELL(1.400 ns) = 1.400 ns; Loc. = PIN_10; Fanout = 47; CLK Node = 'wr'
            Info: 2: + IC(2.600 ns) + CELL(2.500 ns) = 6.500 ns; Loc. = LC2; Fanout = 39; REG Node = 'flag_counter'
            Info: Total cell delay = 3.900 ns ( 60.00 % )
            Info: Total interconnect delay = 2.600 ns ( 40.00 % )
    Info: + Micro clock to output delay of source is 1.600 ns
    Info: + Micro setup delay of destination is 2.900 ns
Info: Clock "clk" has Internal fmax of 71.43 MHz between source register "lpm_counter:counter_rtl_0|dffs[0]" and destination register "serial_og~reg0" (period= 14.0 ns)
    Info: + Longest register to register delay is 9.500 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC7; Fanout = 19; REG Node = 'lpm_counter:counter_rtl_0|dffs[0]'
        Info: 2: + IC(2.400 ns) + CELL(3.900 ns) = 6.300 ns; Loc. = SEXP23; Fanout = 2; COMB Node = 'Mux~600'
        Info: 3: + IC(0.000 ns) + CELL(3.200 ns) = 9.500 ns; Loc. = LC21; Fanout = 3; REG Node = 'serial_og~reg0'
        Info: Total cell delay = 7.100 ns ( 74.74 % )
        Info: Total interconnect delay = 2.400 ns ( 25.26 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk" to destination register is 3.600 ns
            Info: 1: + IC(0.000 ns) + CELL(2.300 ns) = 2.300 ns; Loc. = PIN_37; Fanout = 13; CLK Node = 'clk'
            Info: 2: + IC(0.000 ns) + CELL(1.300 ns) = 3.600 ns; Loc. = LC21; Fanout = 3; REG Node = 'serial_og~reg0'
            Info: Total cell delay = 3.600 ns ( 100.00 % )
        Info: - Longest clock path from clock "clk" to source register is 3.600 ns
            Info: 1: + IC(0.000 ns) + CELL(2.300 ns) = 2.300 ns; Loc. = PIN_37; Fanout = 13; CLK Node = 'clk'
            Info: 2: + IC(0.000 ns) + CELL(1.300 ns) = 3.600 ns; Loc. = LC7; Fanout = 19; REG Node = 'lpm_counter:counter_rtl_0|dffs[0]'
            Info: Total cell delay = 3.600 ns ( 100.00 % )
    Info: + Micro clock to output delay of source is 1.600 ns
    Info: + Micro setup delay of destination is 2.900 ns
Info: tsu for register "flag_low" (data pin = "wr", clock pin = "clk") is 7.400 ns
    Info: + Longest pin to register delay is 8.100 ns
        Info: 1: + IC(0.000 ns) + CELL(1.400 ns) = 1.400 ns; Loc. = PIN_10; Fanout = 47; CLK Node = 'wr'
        Info: 2: + IC(2.600 ns) + CELL(1.200 ns) = 5.200 ns; Loc. = LC56; Fanout = 1; COMB Node = 'flag_low~179'
        Info: 3: + IC(0.000 ns) + CELL(2.900 ns) = 8.100 ns; Loc. = LC57; Fanout = 39; REG Node = 'flag_low'
        Info: Total cell delay = 5.500 ns ( 67.90 % )
        Info: Total interconnect delay = 2.600 ns ( 32.10 % )
    Info: + Micro setup delay of destination is 2.900 ns
    Info: - Shortest clock path from clock "clk" to destination register is 3.600 ns
        Info: 1: + IC(0.000 ns) + CELL(2.300 ns) = 2.300 ns; Loc. = PIN_37; Fanout = 13; CLK Node = 'clk'
        Info: 2: + IC(0.000 ns) + CELL(1.300 ns) = 3.600 ns; Loc. = LC57; Fanout = 39; REG Node = 'flag_low'
        Info: Total cell delay = 3.600 ns ( 100.00 % )
Info: tco from clock "clk" to destination pin "clk_out" through register "clk_out~reg0" is 13.800 ns
    Info: + Longest clock path from clock "clk" to source register is 3.600 ns
        Info: 1: + IC(0.000 ns) + CELL(2.300 ns) = 2.300 ns; Loc. = PIN_37; Fanout = 13; CLK Node = 'clk'
        Info: 2: + IC(0.000 ns) + CELL(1.300 ns) = 3.600 ns; Loc. = LC26; Fanout = 8; REG Node = 'clk_out~reg0'
        Info: Total cell delay = 3.600 ns ( 100.00 % )
    Info: + Micro clock to output delay of source is 1.600 ns
    Info: + Longest register to pin delay is 8.600 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC26; Fanout = 8; REG Node = 'clk_out~reg0'
        Info: 2: + IC(2.300 ns) + CELL(4.500 ns) = 6.800 ns; Loc. = LC17; Fanout = 1; COMB Node = 'clk_out~90'
        Info: 3: + IC(0.000 ns) + CELL(1.800 ns) = 8.600 ns; Loc. = PIN_15; Fanout = 0; PIN Node = 'clk_out'
        Info: Total cell delay = 6.300 ns ( 73.26 % )
        Info: Total interconnect delay = 2.300 ns ( 26.74 % )
Info: Longest tpd from source pin "cpld_sel" to destination pin "sel_out3" is 10.300 ns
    Info: 1: + IC(0.000 ns) + CELL(1.400 ns) = 1.400 ns; Loc. = PIN_42; Fanout = 59; PIN Node = 'cpld_sel'
    Info: 2: + IC(2.600 ns) + CELL(4.500 ns) = 8.500 ns; Loc. = LC1; Fanout = 1; COMB Node = 'sel_out3~13'
    Info: 3: + IC(0.000 ns) + CELL(1.800 ns) = 10.300 ns; Loc. = PIN_6; Fanout = 0; PIN Node = 'sel_out3'
    Info: Total cell delay = 7.700 ns ( 74.76 % )
    Info: Total interconnect delay = 2.600 ns ( 25.24 % )
Info: th for register "temp[7]" (data pin = "din[7]", clock pin = "wr") is 0.900 ns
    Info: + Longest clock path from clock "wr" to destination register is 6.500 ns
        Info: 1: + IC(0.000 ns) + CELL(1.400 ns) = 1.400 ns; Loc. = PIN_10; Fanout = 47; CLK Node = 'wr'
        Info: 2: + IC(2.600 ns) + CE