📄 tiaoping.rpt
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din5 : INPUT;
din6 : INPUT;
din7 : INPUT;
d_sel : INPUT;
p1_3 : INPUT;
p1_4 : INPUT;
p1_5 : INPUT;
p1_6 : INPUT;
rd : INPUT;
sel_addr0 : INPUT;
sel_addr1 : INPUT;
tck : INPUT;
tdi : INPUT;
tdo : INPUT;
tms : INPUT;
wr : INPUT;
-- Node name is 'addr_out0' = ':28'
-- Equation name is 'addr_out0', type is output
addr_out0 = DFFE( count_x0 $ GND, p1_3, VCC, VCC, VCC);
-- Node name is 'addr_out1' = ':30'
-- Equation name is 'addr_out1', type is output
addr_out1 = DFFE( count_x1 $ GND, p1_3, VCC, VCC, VCC);
-- Node name is 'addr_out2' = ':32'
-- Equation name is 'addr_out2', type is output
addr_out2 = DFFE( count_x2 $ GND, p1_3, VCC, VCC, VCC);
-- Node name is 'addr_out3' = ':34'
-- Equation name is 'addr_out3', type is output
addr_out3 = DFFE( count_x3 $ GND, p1_3, VCC, VCC, VCC);
-- Node name is 'clk_out' = ':40'
-- Equation name is 'clk_out', type is output
clk_out = DFFE( _EQ001 $ GND, GLOBAL( clk), VCC, VCC, VCC);
_EQ001 = !count_temp3 & cpld_sel & wr
# clk_out & cpld_sel;
-- Node name is ':55' = 'count_temp0'
-- Equation name is 'count_temp0', location is LC027, type is buried.
count_temp0 = DFFE( _EQ002 $ GND, GLOBAL( clk), VCC, VCC, VCC);
_EQ002 = count_temp0 & count_temp3 & cpld_sel & wr
# !count_temp0 & !count_temp3 & cpld_sel & wr;
-- Node name is ':54' = 'count_temp1'
-- Equation name is 'count_temp1', location is LC028, type is buried.
count_temp1 = DFFE( _EQ003 $ GND, GLOBAL( clk), VCC, VCC, VCC);
_EQ003 = !count_temp0 & count_temp1 & !count_temp3 & cpld_sel & wr
# count_temp0 & !count_temp1 & !count_temp3 & cpld_sel & wr
# count_temp1 & count_temp3 & cpld_sel & wr;
-- Node name is ':53' = 'count_temp2'
-- Equation name is 'count_temp2', location is LC026, type is buried.
count_temp2 = DFFE( _EQ004 $ GND, GLOBAL( clk), VCC, VCC, VCC);
_EQ004 = !count_temp3 & cpld_sel & d_sel & _LC046 & wr
# !count_temp3 & cpld_sel & !d_sel & _LC044 & wr
# count_temp2 & count_temp3 & cpld_sel & wr;
-- Node name is ':52' = 'count_temp3'
-- Equation name is 'count_temp3', location is LC031, type is buried.
count_temp3 = DFFE( _EQ005 $ GND, GLOBAL( clk), VCC, VCC, VCC);
_EQ005 = count_temp0 & count_temp1 & count_temp2 & !count_temp3 &
cpld_sel & wr
# count_temp3 & cpld_sel & wr;
-- Node name is ':59' = 'count_x0'
-- Equation name is 'count_x0', location is LC045, type is buried.
count_x0 = TFFE(!_EQ006, p1_3, VCC, VCC, VCC);
_EQ006 = !count_x0 & cpld_sel & !p1_6;
-- Node name is ':58' = 'count_x1'
-- Equation name is 'count_x1', location is LC039, type is buried.
count_x1 = DFFE( _EQ007 $ _LC043, p1_3, VCC, VCC, VCC);
_EQ007 = cpld_sel & _LC043 & !p1_6;
-- Node name is ':57' = 'count_x2'
-- Equation name is 'count_x2', location is LC038, type is buried.
count_x2 = DFFE( _EQ008 $ _LC042, p1_3, VCC, VCC, VCC);
_EQ008 = cpld_sel & _LC042 & !p1_6;
-- Node name is ':56' = 'count_x3'
-- Equation name is 'count_x3', location is LC034, type is buried.
count_x3 = DFFE( _EQ009 $ _LC041, p1_3, VCC, VCC, VCC);
_EQ009 = cpld_sel & _LC041 & !p1_6;
-- Node name is 'oe_out'
-- Equation name is 'oe_out', location is LC019, type is output.
oe_out = LCELL( p1_4 $ GND);
-- Node name is 'sel_out0'
-- Equation name is 'sel_out0', location is LC004, type is output.
sel_out0 = LCELL( _EQ010 $ GND);
_EQ010 = !cpld_sel & !sel_addr0 & !sel_addr1;
-- Node name is 'sel_out1'
-- Equation name is 'sel_out1', location is LC003, type is output.
sel_out1 = LCELL( _EQ011 $ VCC);
_EQ011 = !cpld_sel & sel_addr0 & !sel_addr1 & !wr
# !cpld_sel & !rd & sel_addr0 & !sel_addr1;
-- Node name is 'sel_out2'
-- Equation name is 'sel_out2', location is LC064, type is output.
sel_out2 = LCELL( _EQ012 $ VCC);
_EQ012 = !cpld_sel & !rd & !sel_addr0 & sel_addr1;
-- Node name is 'sel_out3'
-- Equation name is 'sel_out3', location is LC001, type is output.
sel_out3 = LCELL( _EQ013 $ VCC);
_EQ013 = !cpld_sel & sel_addr0 & sel_addr1 & !wr
# !cpld_sel & !rd & sel_addr0 & sel_addr1;
-- Node name is 'serial_og' = ':26'
-- Equation name is 'serial_og', type is output
serial_og = TFFE( _EQ014, GLOBAL( clk), VCC, VCC, VCC);
_EQ014 = !count_temp3 & cpld_sel & !d_sel & !serial_og & tmp87 & wr
# !count_temp3 & cpld_sel & !d_sel & serial_og & !tmp87 & wr;
-- Node name is 'serial_or' = ':24'
-- Equation name is 'serial_or', type is output
serial_or = TFFE( _EQ015, GLOBAL( clk), VCC, VCC, VCC);
_EQ015 = !count_temp3 & cpld_sel & d_sel & !serial_or & tmp87 & wr
# !count_temp3 & cpld_sel & d_sel & serial_or & !tmp87 & wr;
-- Node name is ':51' = 'tmp80'
-- Equation name is 'tmp80', location is LC030, type is buried.
tmp80 = DFFE( _EQ016 $ GND, GLOBAL( clk), VCC, VCC, VCC);
_EQ016 = cpld_sel & tmp80 & wr
# cpld_sel & din0 & !wr;
-- Node name is ':50' = 'tmp81'
-- Equation name is 'tmp81', location is LC025, type is buried.
tmp81 = DFFE( _EQ017 $ GND, GLOBAL( clk), VCC, VCC, VCC);
_EQ017 = count_temp3 & cpld_sel & tmp81 & wr
# !count_temp3 & cpld_sel & tmp80 & wr
# cpld_sel & din1 & !wr;
-- Node name is ':49' = 'tmp82'
-- Equation name is 'tmp82', location is LC029, type is buried.
tmp82 = DFFE( _EQ018 $ GND, GLOBAL( clk), VCC, VCC, VCC);
_EQ018 = count_temp3 & cpld_sel & tmp82 & wr
# !count_temp3 & cpld_sel & tmp81 & wr
# cpld_sel & din2 & !wr;
-- Node name is ':48' = 'tmp83'
-- Equation name is 'tmp83', location is LC032, type is buried.
tmp83 = DFFE( _EQ019 $ GND, GLOBAL( clk), VCC, VCC, VCC);
_EQ019 = count_temp3 & cpld_sel & tmp83 & wr
# !count_temp3 & cpld_sel & tmp82 & wr
# cpld_sel & din3 & !wr;
-- Node name is ':47' = 'tmp84'
-- Equation name is 'tmp84', location is LC018, type is buried.
tmp84 = DFFE( _EQ020 $ GND, GLOBAL( clk), VCC, VCC, VCC);
_EQ020 = count_temp3 & cpld_sel & tmp84 & wr
# !count_temp3 & cpld_sel & tmp83 & wr
# cpld_sel & din4 & !wr;
-- Node name is ':46' = 'tmp85'
-- Equation name is 'tmp85', location is LC022, type is buried.
tmp85 = DFFE( _EQ021 $ GND, GLOBAL( clk), VCC, VCC, VCC);
_EQ021 = count_temp3 & cpld_sel & tmp85 & wr
# !count_temp3 & cpld_sel & tmp84 & wr
# cpld_sel & din5 & !wr;
-- Node name is ':45' = 'tmp86'
-- Equation name is 'tmp86', location is LC024, type is buried.
tmp86 = DFFE( _EQ022 $ GND, GLOBAL( clk), VCC, VCC, VCC);
_EQ022 = count_temp3 & cpld_sel & tmp86 & wr
# !count_temp3 & cpld_sel & tmp85 & wr
# cpld_sel & din6 & !wr;
-- Node name is ':44' = 'tmp87'
-- Equation name is 'tmp87', location is LC023, type is buried.
tmp87 = DFFE( _EQ023 $ GND, GLOBAL( clk), VCC, VCC, VCC);
_EQ023 = count_temp3 & cpld_sel & tmp87 & wr
# !count_temp3 & cpld_sel & tmp86 & wr
# cpld_sel & din7 & !wr;
-- Node name is 'xlat'
-- Equation name is 'xlat', location is LC033, type is output.
xlat = LCELL( p1_3 $ GND);
-- Node name is '|LPM_ADD_SUB:879|addcore:adder|addcore:adder0|result_node2' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC046', type is buried
_LC046 = LCELL( count_temp2 $ _EQ024);
_EQ024 = count_temp0 & count_temp1;
-- Node name is '|LPM_ADD_SUB:1439|addcore:adder|addcore:adder0|result_node2' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC044', type is buried
_LC044 = LCELL( count_temp2 $ _EQ025);
_EQ025 = count_temp0 & count_temp1;
-- Node name is '|LPM_ADD_SUB:2121|addcore:adder|addcore:adder0|result_node1' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC043', type is buried
_LC043 = LCELL( count_x1 $ count_x0);
-- Node name is '|LPM_ADD_SUB:2121|addcore:adder|addcore:adder0|result_node2' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC042', type is buried
_LC042 = LCELL( count_x2 $ _EQ026);
_EQ026 = count_x0 & count_x1;
-- Node name is '|LPM_ADD_SUB:2121|addcore:adder|addcore:adder0|result_node3' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC041', type is buried
_LC041 = LCELL( count_x3 $ _EQ027);
_EQ027 = count_x0 & count_x1 & count_x2;
-- Shareable expanders that are duplicated in multiple LABs:
-- (none)
Project Information d:\vhdl\tiaoping\tiaoping.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = on
Rules = EPLD Rules
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:01
Fitter 00:00:00
Timing SNF Extractor 00:00:00
Assembler 00:00:00
Design Doctor 00:00:03
-------------------------- --------
Total Time 00:00:04
Memory Allocated
-----------------
Peak memory allocated during compilation = 5,283K
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