_primary.vhd

来自「精简的sdram读写控制器例子」· VHDL 代码 · 共 14 行

library verilog;
use verilog.vl_types.all;
entity v51 is
    port(
        clk             : in     vl_logic;
        data51          : out    vl_logic_vector(7 downto 0);
        ctl51           : out    vl_logic;
        adr51           : out    vl_logic_vector(3 downto 0);
        clk51           : out    vl_logic;
        rst             : out    vl_logic;
        int51           : in     vl_logic
    );
end v51;