_primary.vhd

来自「精简的sdram读写控制器例子」· VHDL 代码 · 共 31 行

library verilog;
use verilog.vl_types.all;
entity fpga is
    generic(
        addr_bits       : integer := 11;
        data_bits       : integer := 16;
        col_bits        : integer := 8;
        mem_sizes       : integer := 524287;
        mode_bits       : integer := 11
    );
    port(
        clk100m         : in     vl_logic;
        data51          : in     vl_logic_vector(7 downto 0);
        ctl51           : in     vl_logic;
        adr51           : in     vl_logic_vector(3 downto 0);
        clk51           : in     vl_logic;
        rst             : in     vl_logic;
        int51           : out    vl_logic;
        datatest        : out    vl_logic_vector(15 downto 0);
        \sdram_Dq_\     : inout  vl_logic_vector;
        \sdram_Addr_\   : out    vl_logic_vector;
        \sdram_Ba_\     : out    vl_logic;
        sdram_clk       : out    vl_logic;
        \sdram_Cs_n_\   : out    vl_logic;
        \sdram_Ras_n_\  : out    vl_logic;
        \sdram_Cas_n_\  : out    vl_logic;
        \sdram_We_n_\   : out    vl_logic;
        \sdram_Dqm_\    : out    vl_logic
    );
end fpga;