t_combo_str.v

来自「Systemverilog 编写的贩卖机代码」· Verilog 代码 · 共 26 行

//'timescale 1ns/100ps
module t_Combo_str();
	reg	a,b,c,d;
	
	wire	w1,w2,w3,w4;
reg y1;
wire y;
always @(y) y1 <= y;
	Combo_str M1(.y(y),
			 .a(a),
			 .b(b),
			 .c(c),
			 .d(d)
			);
	initial begin
		#100 $finish;
	end
	initial begin
	$display($time, " << Starting the Simulation >>");
	#10 a=0;b=0;c=0;d=0;
	#10 b=1;c=1;d=1;
	#10 c=1;d=0;
end
endmodule