can_counter.v

来自「Systemverilog 编写的贩卖机代码」· Verilog 代码 · 共 20 行

// Verilog HDL for gdglib, can_counter _functional

module can_counter( clk, load, count, dispense, empty);

	input       clk, load, dispense;
	input [7:0] count;
	output      empty;

	reg [7:0]   left; 

	wire        empty = |left;

	always @(negedge clk)
		if (load && !dispense)
			left <= count;
		else if(!load && dispense)
			left <= left - 1;

endmodule