counter _team.v.bak

实用闹钟的verilog代码。不是vhdl的！经过ldv验证

module COUNTER_TEAM (out tri [27:0] q_clock,
											input clk , for_bac_control , 
											input [3:0] buf_out, buf_in ,
											input vectored [6:0] pre_h , clr_h , syn_per_h , syn_clr_h ,
						  						 							 	 pre_m , clr_m , syn_per_m , syn_clr_m ,
																					 pre_s , clr_s , syn_per_s , syn_clr_s ,
																					 pre_ms , clr_ms , syn_per_ms , syn_clr_ms);
									
	wire [6:0]	pre_h_inside , clr_h_inside , syn_per_h_inside , syn_clr_h_inside ,
							pre_m_inside , clr_m_inside , syn_per_m_inside , syn_clr_m_inside ,
							pre_s_inside , clr_s_inside , syn_per_s_inside , syn_clr_s_inside ,
							pre_ms_inside , clr_ms_inside , syn_per_ms_inside , syn_clr_ms_inside ;
	wire [6:0]  pre_h_outside , clr_h_outside , syn_per_h_outside , syn_clr_h_outside ,    
              pre_m_outside , clr_m_outside , syn_per_m_outside , syn_clr_m_outside ,    
              pre_s_outside , clr_s_outside , syn_per_s_outside , syn_clr_s_outside ,    
              pre_ms_outside , clr_ms_outside , syn_per_ms_outside , syn_clr_ms_outside ;








endmoudle




moudle	DATAIN_BUS_CONTROL (output reg [6:0]  pre_h_inside , clr_h_inside , syn_per_h_inside , syn_clr_h_inside ,
							  							 			  		 pre_m_inside , clr_m_inside , syn_per_m_inside , syn_clr_m_inside ,
																				 	 pre_s_inside , clr_s_inside , syn_per_s_inside , syn_clr_s_inside ,
																					 pre_ms_inside , clr_ms_inside , syn_per_ms_inside , syn_clr_ms_inside ,
												input vectored [6:0] pre_h , clr_h , syn_per_h , syn_clr_h ,
							  						 							 	 pre_m , clr_m , syn_per_m , syn_clr_m ,
																						 pre_s , clr_s , syn_per_s , syn_clr_s ,
																						 pre_ms , clr_ms , syn_per_ms , syn_clr_ms ,
													input control  pre_h_c , clr_h_c , syn_per_h_c , syn_clr_h_c ,
							  							 					 pre_m_c , clr_m_c , syn_per_m_c , syn_clr_m_c ,
																				 pre_s_c , clr_s_c , syn_per_s_c , syn_clr_s_c ,
																				 pre_ms_c , clr_ms_c , syn_per_ms_c , syn_clr_ms_c );
																			
		 	 bufif0	(	pre_h_inside , 		pre_h , 	pre_h_c )	; 
			 bufif0	(	pre_m_inside , 		pre_m , 	pre_m_c ) ;
			 bufif0	(	pre_s_inside , 		pre_s , 	pre_s_c ) ;
			 bufif0	( pre_ms_inside ,		pre_ms ,	pre_ms_c )	;
		
			 bufif0	(	clr_h_inside ,  	clr_h ,  	clr_h_c )  ;
			 bufif0	(	clr_m_inside ,   	clr_m , 	clr_m_c )  ;
			 bufif0	(	clr_s_inside ,   	clr_s ,  	clr_s_c )	 ;   
			 bufif0	(	clr_ms_inside ,  	clr_ms ,	clr_ms_c ) 	;

			 bufif0	(	syn_per_h_inside , 		syn_per_h ,    	syn_per_h_c )  ; 
			 bufif0	(	syn_per_m_inside , 		syn_per_m ,    	syn_per_m_c )  ; 
			 bufif0	(	syn_per_s_inside , 		syn_per_s ,    	syn_per_s_c )  ; 
			 bufif0	(	syn_per_ms_inside ,		syn_per_ms , 		syn_per_ms_c ) 	;

			 bufif0	(	syn_clr_h_inside ,    syn_clr_h ,  		syn_clr_h_c )	;
			 bufif0	(	syn_clr_m_inside ,    syn_clr_m ,  		syn_clr_m_c )	;
			 bufif0	(	syn_clr_s_inside ,    syn_clr_s ,  		syn_clr_s_c )	;
 			 bufif0	(	syn_clr_ms_inside , 	syn_clr_ms ,		syn_clr_ms_c )	;







endmodule



moudle	()	;

endmoudle





moudle COUNTER_0TO60	(output tri  [6:0] 60.q ,
											input clk ,
											input for_bac_control,
											input vectored [6:0]	pre , clr , syn_per , syn_clr);

wire [6:0]	q , Q  ,
						j_for , k_for ,
						j_bac , k_bac ,
					  j , k  ;
					   

	
	assign 60.q = q ;

	
	
	J_K_FF	JK6	(.q(q[6]) .j(j[6]) .k(k[6]) .pre(pre[6]) .clr(clr[6])
							 .syn_pre(syn_pre[6]) .syn_clr(syn_clr[6]) .clk(clk) ); 
	
	assign j_for[6] = q[4] & q[5] ;
	//assign k_for[6] = q[4] ;

	assign j_bac[6] = q[4] & (~q[5]) ;
	//assign k_bac[6] = q[4] ;


	assign k[6] = q[4]	;
	assign j[6] = for_bac_control ? j_for[6] : j_bac[6] ;



	
	J_K_FF	JK5	(.q(q[5]) .j(j[5]) .k(k[5]) .pre(pre[5]) .clr(clr[5])
							 .syn_pre(syn_pre[5]) .syn_clr(syn_clr[5]) .clk(clk) );
	
	assign j_for[5] = q[6] & q[4] ;
	//assign k_for[5] = q[4];
	
	assign j_bac[5] = (~q[6]) & q[4]	;
	//assign k_bac[5] = q[4]	;

	
	assign k [5] = q[4] ;	
	assign j [5] =  for_bac_control ? j_for[5] : j_bac[5] ;	
	

	
	J_K_FF	JK4	(.q(q[4]) .j(j[4]) .k(k[4]) .pre(pre[4]) .clr(clr[4])
							 .syn_pre(syn_pre[4]) .syn_clr(syn_clr[4]) .clk(clk) );
	
	assign j_for[4] = q[0] & q[3] ;
	assign k_for[4] = j_for[4] ;

	assign j_bac[4] = ~( q[0] + q[1] + q[2] + q[3] );
	assign k_bac[4] = j_bac[4]	;
	
	assign j[4] = for_bac_control ? j_for[4] : j_bac[4] ;
	assign k[4] = for_bac_control ? k_for[4] : k_bac[4] ;
	
	
	 	
	J_K_FF	JK3	(.q(q[3]) .j(j[3]) .k(k[3]) .pre(pre[3]) .clr(clr[3])
							 .syn_pre(syn_pre[3]) .syn_clr(syn_clr[3]) .clk(clk) );
	
	assign j_for[3] = q[0] & q[1] & q[2] ;
	//assign k_for[3] = q[0] ;
	
	assign j_bac[3] = q[3] & q[0] ;
	//assign k_bac[3] = q[0]	;
	
	assign k[3] = q[0]	;
	assign j[3] = for_bac_control ? j_for[3] : j_bac[3]	;
	
	
	J_K_FF	JK2	(.q(q[2]) .j(j[2]) .k(k[2]) .pre(pre[2]) .clr(clr[2])
							 .syn_pre(syn_pre[2]) .syn_clr(syn_clr[2]) .clk(clk) );
	
	assign j_for[2] = q[1] & q[0] ;
	assign k_for[2] = j[2] ;
	
	assign j_bac[2] = q[0] & (~q[2]);
	assign k_bac[2] = q[0] & q[2] ;
	
	assign j[2] = for_bac_control ? j_for[2] : j_bac[2] ;
	assign k[2] = for_bac_control ? k_for[2] : k_bac[2]	;
	
	
	J_K_FF	JK1	(.q(q[1])  .j(j[1]) .k(k[1]) .pre(pre[1]) .clr(clr[1])
							 .syn_pre(syn_pre[1]) .syn_clr(syn_clr[1]) .clk(clk) );
	
	assign j[1] = q[0] & (~q[3]);
	assign k[1] = q[0];
	
	//assign j_for[1] = q[0] & (~q[3]);
	//assign k_for[1] = q[0];
	//assgin j_bac[1] = q[0] & ~(q[3]);
	//assign k_bac[1] = q[0] ;
	
	
	
	
	J_K_FF	JK0	(.q(q[0]) .j(j[0]) .k(k[0]) .pre(pre[0]) .clr(clr[0])
							 .syn_pre(syn_pre[0]) .syn_clr(syn_clr[0]) .clk(clk) );
	
	assign j[0]=k[0]=1;   
	
	
endmoudle







primitive J_K_FF (output reg q ,									//sync & async
							 output reg Q,
							 input j, k,
							 input pre , clr,
							 input syn_pre,syn_clr,
							 input clk );

table

	//		j		k		pre		clr		syn_per		syn_clr		clk			q  state  next			
				?		?		1			0				?					?				?				:		?		:	 0	;
				?		?		0			0				?					?				?				:		?		:	 0	;
				?		?		0			1				?					?				?				:		?	  :   1	;
				
				
				
				?		?		1			1				0					1			 	f				:		?		:	 1	;	
				?		?		1			1				1					0			 	f				:		?		:	 0	;
				?		?		1			1				0					0			 	f				:		?		:	 1	;
				
				?		?		1			1				0					1		  (?0)			:		?		:	 -	;	
				?		?		1			1				1					0		  (?0)			:		?		:	 -	;
				?		?		1			1				0					0			(?0)			:		?		:	 -	;
				
				?		?		1			1				0					1		  (11)			:		?		:	-		;
				?		?		1			1				1					0		  (11)			:		?		:	-		;
				?		?		1			1				0					0			(11)			:		?		:	-		;
				
				//?		?		1			1				0					1		  	r				:				
				//?		?		1			1				1					0		  	r				:	
				//?		?		1			1				0					0				r				:	
				
				
				
				
				0		0		1			1				1					1				f				:		1		:	0		;
				0		0		1			1				1					1				f				:		0		:	1		;
				
				1		0		1			1				1					1			 	f				:		?		:	1		;
	   		0		1		1			1				1					1			 	f				:		?		:	0		;
   			
   			1		1		1			1				1					1				f				:		?		:	-		;
				
				
				0		0		1			1				1					1			(?0)			:		?		:	-		;	
				1		0		1			1				1					1			(?0)			:		?		:	-		;
	   		0		1		1			1				1					1			(?0)			:		?		:	-		;
   			1		1		1			1				1					1			(?0)			:		?		:	-		;	
				
				0		0		1			1				1					1			(11)			:		?		:	-		;
				1		0		1			1				1					1			(11)			:		?		:	-		;
	   		0		1		1			1				1					1			(11)			:		?		:	-		;
   			1		1		1			1				1					1			(11)			:		?		:	-		;
   			
   			//0		0		1			1				1					1				r			:	
				//1		0		1			1				1					1			 	r			:	
	   		//0		1		1			1				1					1			 	r			:		
   			//1		1		1			1				1					1				r			:		
						
				
endprimitive