clock.vhd

用VHDL编写的数字时钟,可变宽度脉冲产生器

ENTITY clock IS
PORT 
( 
  clk  :IN BIT;
  SET1 :IN BIT;
  SET2 :IN BIT;
  SECH :OUT INTEGER RANGE 0 TO 15;
  SECL :OUT INTEGER RANGE 0 TO 15;
  MINH :OUT INTEGER RANGE 0 TO 15;
  MINL :OUT INTEGER RANGE 0 TO 15;
  HOUH :OUT INTEGER RANGE 0 TO 15;
  HOUL :OUT INTEGER RANGE 0 TO 15
);
END clock;
ARCHITECTURE a OF clock IS
BEGIN
PROCESS (clk)
		VARIABLE	sl,sh,ml,mh,hl,hh	: INTEGER RANGE 0 TO 15;	
BEGIN
IF (clk'EVENT AND clk = '1') THEN
	IF SET1 = '0' AND SET2='0' THEN
			
		
		IF (sl=9) THEN 
		 sl:=0;
			if(sh=5) THEN
			sh:=0;
					if(ml=9) then
					ml:=0;
						if(mh=5) then
						mh:=0;
							if(hh=2 and hl=4) then
								hh:=0;hl:=0;mh:=0;ml:=0;sh:=0;sl:=0;
							else 
									if(hl=9) then
									hl:=0;
									hh:=hh+1;
									else
									hl:=hl+1;
									end if;
							end if;						
						else
						mh:=mh+1;
						end if;
							
					else
					ml:=ml+1;
					end if;
															
			else
			sh:=sh+1;
			end if;
		
		 else 
		 sl:=sl+1;
		
		
		END IF;
		
	END IF;
  IF(SET1='1') THEN
		ml:=ml+1;
		if(ml=10)then
			ml:=0;
			mh:=mh+1;
				if(mh=6)then
					mh:=0;
					ml:=0;
				end if;
		end if;
  END IF;
  IF(SET2='1') THEN
		hl:=hl+1;
	if(hl=10 and hh<2)then
			hl:=0;
			hh:=hh+1;
	
	end if;
		
			
  END IF;
	if(hl=4 and hh=2) then
	hh:=0;
	hl:=0;
	end if;
	
END IF;
		SECL<=sl;
		SECH<=sh;
		MINH<=mh;
		MINL<=ml;
		HOUH<=hh;
		HOUL<=hl;
END PROCESS;

END a;