simpsig.vhd

来自「用VHDL编写的数字时钟,可变宽度脉冲产生器」· VHDL 代码 · 共 21 行

-- MAX+plus II VHDL Example
-- Simple Signal Assignment
-- Copyright (c) 1994 Altera Corporation

ENTITY simpsig IS
	PORT
	(
		a, b, e	: IN  BIT;
		c, d	: OUT BIT
	);
END simpsig;

ARCHITECTURE maxpld OF simpsig IS
BEGIN

	c <= a AND b;
	d <= e;
	
END maxpld;