adder_1.vhd

用VHDL编写的数字时钟,可变宽度脉冲产生器

entity xor2 is
port(x,y:in bit;z:out bit);
end;
architecture one of xor2 is
begin
z<=x xor y;
end one;
entity and_2 is
port(x,y:in bit;z:out bit);
end;
architecture one of and_2 is
begin
z<=x and y;
end one;

entity adder_1 is 
port(a,b:in bit:='0';sum,cry:out bit);
end;
architecture one of adder_1 is
component xor2
port(x,y:in bit;z:out bit);
end component;
component and_2
port(x,y:in bit;z:out bit);
end component;
begin
x1: xor2 port map(a,b,sum);
A1: and_2 port map(a,b,cry);
end;