test.vhd

用VHDL编写的数字时钟,可变宽度脉冲产生器

library ieee;
use ieee.std_logic_1164.all;
entity test is port(a,b:in bit_vector(1 downto 0);a_less_than_b:out bit);
end;
architecture behave of test is
begin
process(a)
variable i:integer;
begin
a_less_than_b<='0';
for i in 1 downto 0 loop
if(a(i)='1'and b(i)='0')then
a_less_than_b<='0';
exit;
elsif(a(i)='0'and b(i)='1')then
a_less_than_b<='1';
exit;
else
next;
end if;
el:end loop;
end process;
end;