condsig.vhd

来自「用VHDL编写的数字时钟,可变宽度脉冲产生器」· VHDL 代码 · 共 20 行

-- MAX+plus II VHDL Example
-- Conditional Signal Assignment
-- Copyright (c) 1994 Altera Corporation

ENTITY condsig IS
	PORT
	(
		input0, input1, sel	: IN  BIT;
		output				: OUT BIT
	);
END condsig;

ARCHITECTURE maxpld OF condsig IS
BEGIN

	output <= input0 WHEN sel = '0' ELSE input1;
		
END maxpld;