clkf.vhd

来自「用VHDL编写的数字时钟,可变宽度脉冲产生器」· VHDL 代码 · 共 14 行

entity clkf is port(x1,x2:in bit;z:out bit:='0');
end ;
architecture behave of clkf is
signal y1,y2:bit:='0';
signal u1,u2:bit:='0';
begin
u2<=(x2 and y2)or((not x2) and (not x1) and y1);
u1<=x1 or ((not x2) and y1) or( (not y2 )and y1);
y1<=u1;
y2<=u2;
z<=x2 and y2;
end;