📄 my_74ls138.rpt
字号:
- 5 - C 09 OR2 3 1 1 0 :525
- 7 - C 09 OR2 3 1 1 0 :531
- 2 - C 06 OR2 3 1 1 0 :537
- 1 - C 08 OR2 3 1 1 0 :543
- 8 - C 09 OR2 3 1 1 0 :549
- 6 - C 09 OR2 3 1 1 0 :555
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: f:\maxplus_study\tt\my_74ls138\my_74ls138.rpt
my_74ls138
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 8/ 96( 8%) 3/ 48( 6%) 0/ 48( 0%) 5/16( 31%) 4/16( 25%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
07: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
10: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: f:\maxplus_study\tt\my_74ls138\my_74ls138.rpt
my_74ls138
** EQUATIONS **
A : INPUT;
B : INPUT;
C : INPUT;
G1 : INPUT;
G2A : INPUT;
G2B : INPUT;
-- Node name is 'y0'
-- Equation name is 'y0', type is output
y0 = _LC6_C9;
-- Node name is 'y1'
-- Equation name is 'y1', type is output
y1 = _LC8_C9;
-- Node name is 'y2'
-- Equation name is 'y2', type is output
y2 = _LC1_C8;
-- Node name is 'y3'
-- Equation name is 'y3', type is output
y3 = _LC2_C6;
-- Node name is 'y4'
-- Equation name is 'y4', type is output
y4 = _LC7_C9;
-- Node name is 'y5'
-- Equation name is 'y5', type is output
y5 = _LC5_C9;
-- Node name is 'y6'
-- Equation name is 'y6', type is output
y6 = _LC3_C9;
-- Node name is 'y7'
-- Equation name is 'y7', type is output
y7 = _LC1_C9;
-- Node name is ':104'
-- Equation name is '_LC2_C9', type is buried
!_LC2_C9 = _LC2_C9~NOT;
_LC2_C9~NOT = LCELL( _EQ001);
_EQ001 = !G1
# G2A
# G2B;
-- Node name is ':513'
-- Equation name is '_LC1_C9', type is buried
_LC1_C9 = LCELL( _EQ002);
_EQ002 = !C
# !B
# !A
# !_LC2_C9;
-- Node name is ':519'
-- Equation name is '_LC3_C9', type is buried
_LC3_C9 = LCELL( _EQ003);
_EQ003 = !B
# A
# !C
# !_LC2_C9;
-- Node name is ':525'
-- Equation name is '_LC5_C9', type is buried
_LC5_C9 = LCELL( _EQ004);
_EQ004 = B
# !A
# !C
# !_LC2_C9;
-- Node name is ':531'
-- Equation name is '_LC7_C9', type is buried
_LC7_C9 = LCELL( _EQ005);
_EQ005 = B
# A
# !C
# !_LC2_C9;
-- Node name is ':537'
-- Equation name is '_LC2_C6', type is buried
_LC2_C6 = LCELL( _EQ006);
_EQ006 = !B
# !A
# C
# !_LC2_C9;
-- Node name is ':543'
-- Equation name is '_LC1_C8', type is buried
_LC1_C8 = LCELL( _EQ007);
_EQ007 = !B
# A
# C
# !_LC2_C9;
-- Node name is ':549'
-- Equation name is '_LC8_C9', type is buried
_LC8_C9 = LCELL( _EQ008);
_EQ008 = B
# !A
# C
# !_LC2_C9;
-- Node name is ':555'
-- Equation name is '_LC6_C9', type is buried
_LC6_C9 = LCELL( _EQ009);
_EQ009 = !_LC2_C9
# C
# B
# A;
Project Information f:\maxplus_study\tt\my_74ls138\my_74ls138.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:02
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 13,054K
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