my_74ls138.vhd

来自「大学vhdl语言实验大全,基于max-plus2平台,内有8-3译码器,8位加法」· VHDL 代码 · 共 39 行

-- MAX+plus II VHDL 
-- Clearable my_74LS138

LIBRARY IEEE;
USE ieee.std_logic_1164.all;


ENTITY my_74LS138 IS
	PORT(
		 G1, G2A,G2B,C,B,A		: IN	STD_LOGIC;
		 y				    : OUT	STD_LOGIC_VECTOR(7 downto 0));
         
END my_74LS138;
 
ARCHITECTURE behave OF my_74LS138 IS
	SIGNAL indata: STD_LOGIC_VECTOR(2 downto 0);
    BEGIN
      indata<=C&B&A;
      P1:process(indata,G1,G2A,G2B)
         begin 
           if(G1='1'and G2A='0'and G2B='0')then
            case indata is
               when "000"=>y<="11111110";
               when "001"=>y<="11111101";
               when "010"=>y<="11111011";
               when "011"=>y<="11110111";
               when "100"=>y<="11101111";
               when "101"=>y<="11011111";
               when "110"=>y<="10111111";
               when "111"=>y<="01111111";
               when others=>y<="XXXXXXXX";
            end case;
          else 
               y<="11111111";
          end if;
         end process;
        END behave;