📄 display.rpt
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03: 3/24( 12%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
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13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
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21: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
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24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: e:\tt\tt\display\display.rpt
display
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 4 clk
Device-Specific Information: e:\tt\tt\display\display.rpt
display
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 5 res
Device-Specific Information: e:\tt\tt\display\display.rpt
display
** EQUATIONS **
clk : INPUT;
res : INPUT;
-- Node name is 'a'
-- Equation name is 'a', type is output
a = _LC3_A3;
-- Node name is 'b'
-- Equation name is 'b', type is output
b = _LC5_A3;
-- Node name is 'c'
-- Equation name is 'c', type is output
c = _LC7_A3;
-- Node name is 'd'
-- Equation name is 'd', type is output
d = _LC1_A3;
-- Node name is 'e'
-- Equation name is 'e', type is output
e = _LC2_A12;
-- Node name is 'f'
-- Equation name is 'f', type is output
f = _LC4_A3;
-- Node name is 'g'
-- Equation name is 'g', type is output
g = _LC6_A6;
-- Node name is 'p1'
-- Equation name is 'p1', type is output
p1 = !_LC1_A1;
-- Node name is 'p2'
-- Equation name is 'p2', type is output
p2 = !_LC3_A1;
-- Node name is 'p3'
-- Equation name is 'p3', type is output
p3 = !_LC2_A1;
-- Node name is 'p4'
-- Equation name is 'p4', type is output
p4 = !_LC4_A1;
-- Node name is 'p5'
-- Equation name is 'p5', type is output
p5 = !_LC6_A3;
-- Node name is 'p6'
-- Equation name is 'p6', type is output
p6 = !_LC2_A3;
-- Node name is 'p7'
-- Equation name is 'p7', type is output
p7 = !_LC8_A3;
-- Node name is 'p8'
-- Equation name is 'p8', type is output
p8 = _LC5_A6;
-- Node name is '|MY_COUNT4:1|:10' = '|MY_COUNT4:1|data0'
-- Equation name is '_LC1_A6', type is buried
_LC1_A6 = DFFE(!_LC1_A6, GLOBAL(!clk), res, VCC, VCC);
-- Node name is '|MY_COUNT4:1|:9' = '|MY_COUNT4:1|data1'
-- Equation name is '_LC3_A6', type is buried
_LC3_A6 = DFFE( _EQ001, GLOBAL(!clk), res, VCC, VCC);
_EQ001 = _LC1_A6 & !_LC3_A6 & !_LC8_A6
# !_LC1_A6 & _LC3_A6 & !_LC8_A6;
-- Node name is '|MY_COUNT4:1|:8' = '|MY_COUNT4:1|data2'
-- Equation name is '_LC2_A6', type is buried
_LC2_A6 = DFFE( _EQ002, GLOBAL(!clk), res, VCC, VCC);
_EQ002 = !_LC1_A6 & _LC2_A6 & !_LC8_A6
# _LC2_A6 & !_LC3_A6 & !_LC8_A6
# _LC1_A6 & !_LC2_A6 & _LC3_A6 & !_LC8_A6;
-- Node name is '|MY_COUNT4:1|:7' = '|MY_COUNT4:1|data3'
-- Equation name is '_LC4_A6', type is buried
_LC4_A6 = DFFE( _EQ003, GLOBAL(!clk), res, VCC, VCC);
_EQ003 = _LC4_A6 & !_LC5_A6 & !_LC8_A6
# !_LC4_A6 & _LC5_A6 & !_LC8_A6;
-- Node name is '|MY_COUNT4:1|LPM_ADD_SUB:61|addcore:adder|:63' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC5_A6', type is buried
_LC5_A6 = LCELL( _EQ004);
_EQ004 = _LC1_A6 & _LC2_A6 & _LC3_A6;
-- Node name is '|MY_COUNT4:1|:50'
-- Equation name is '_LC8_A6', type is buried
!_LC8_A6 = _LC8_A6~NOT;
_LC8_A6~NOT = LCELL( _EQ005);
_EQ005 = !_LC2_A6
# !_LC7_A6
# !_LC1_A6
# !res;
-- Node name is '|7448:39|:69' = '|7448:39|OA'
-- Equation name is '_LC3_A3', type is buried
_LC3_A3 = LCELL( _EQ006);
_EQ006 = _LC1_A6 & _LC2_A6 & !_LC3_A6
# _LC1_A6 & _LC2_A6 & !_LC4_A6
# _LC1_A6 & !_LC3_A6 & _LC4_A6
# !_LC2_A6 & !_LC3_A6 & _LC4_A6
# _LC1_A6 & _LC3_A6 & !_LC4_A6
# !_LC2_A6 & _LC3_A6 & !_LC4_A6
# !_LC1_A6 & !_LC2_A6 & !_LC3_A6
# !_LC1_A6 & !_LC2_A6 & !_LC4_A6;
-- Node name is '|7448:39|:68' = '|7448:39|OB'
-- Equation name is '_LC5_A3', type is buried
_LC5_A3 = LCELL( _EQ007);
_EQ007 = !_LC1_A6 & !_LC3_A6
# _LC1_A6 & _LC3_A6 & !_LC4_A6
# !_LC2_A6 & !_LC3_A6
# !_LC2_A6 & !_LC4_A6;
-- Node name is '|7448:39|:70' = '|7448:39|OC'
-- Equation name is '_LC7_A3', type is buried
_LC7_A3 = LCELL( _EQ008);
_EQ008 = !_LC2_A6 & !_LC3_A6
# _LC1_A6 & !_LC2_A6
# _LC2_A6 & !_LC4_A6
# !_LC3_A6 & !_LC4_A6
# _LC1_A6 & !_LC4_A6;
-- Node name is '|7448:39|:67' = '|7448:39|OD'
-- Equation name is '_LC1_A3', type is buried
_LC1_A3 = LCELL( _EQ009);
_EQ009 = !_LC2_A6 & _LC3_A6
# _LC1_A6 & _LC2_A6 & !_LC3_A6
# !_LC1_A6 & !_LC2_A6
# !_LC1_A6 & _LC3_A6;
-- Node name is '|7448:39|:71' = '|7448:39|OE'
-- Equation name is '_LC2_A12', type is buried
_LC2_A12 = LCELL( _EQ010);
_EQ010 = !_LC1_A6 & !_LC2_A6
# !_LC1_A6 & _LC3_A6;
-- Node name is '|7448:39|:66' = '|7448:39|OF'
-- Equation name is '_LC4_A3', type is buried
_LC4_A3 = LCELL( _EQ011);
_EQ011 = _LC2_A6 & !_LC3_A6
# !_LC3_A6 & _LC4_A6
# !_LC1_A6 & _LC2_A6
# !_LC1_A6 & !_LC3_A6;
-- Node name is '|7448:39|:72' = '|7448:39|OG'
-- Equation name is '_LC6_A6', type is buried
_LC6_A6 = LCELL( _EQ012);
_EQ012 = _LC2_A6 & !_LC5_A6
# _LC4_A6 & !_LC5_A6
# _LC3_A6 & !_LC5_A6;
-- Node name is '|7448:39|:34'
-- Equation name is '_LC7_A6', type is buried
!_LC7_A6 = _LC7_A6~NOT;
_LC7_A6~NOT = LCELL( _EQ013);
_EQ013 = !_LC3_A6
# !_LC4_A6;
-- Node name is '|74138:12|:15' = '|74138:12|Y0N'
-- Equation name is '_LC1_A1', type is buried
!_LC1_A1 = _LC1_A1~NOT;
_LC1_A1~NOT = LCELL( _EQ014);
_EQ014 = !_LC1_A6 & !_LC2_A6 & !_LC3_A6;
-- Node name is '|74138:12|:16' = '|74138:12|Y1N'
-- Equation name is '_LC3_A1', type is buried
!_LC3_A1 = _LC3_A1~NOT;
_LC3_A1~NOT = LCELL( _EQ015);
_EQ015 = _LC1_A6 & !_LC2_A6 & !_LC3_A6;
-- Node name is '|74138:12|:17' = '|74138:12|Y2N'
-- Equation name is '_LC2_A1', type is buried
!_LC2_A1 = _LC2_A1~NOT;
_LC2_A1~NOT = LCELL( _EQ016);
_EQ016 = !_LC1_A6 & !_LC2_A6 & _LC3_A6;
-- Node name is '|74138:12|:18' = '|74138:12|Y3N'
-- Equation name is '_LC4_A1', type is buried
!_LC4_A1 = _LC4_A1~NOT;
_LC4_A1~NOT = LCELL( _EQ017);
_EQ017 = _LC1_A6 & !_LC2_A6 & _LC3_A6;
-- Node name is '|74138:12|:19' = '|74138:12|Y4N'
-- Equation name is '_LC6_A3', type is buried
!_LC6_A3 = _LC6_A3~NOT;
_LC6_A3~NOT = LCELL( _EQ018);
_EQ018 = !_LC1_A6 & _LC2_A6 & !_LC3_A6;
-- Node name is '|74138:12|:20' = '|74138:12|Y5N'
-- Equation name is '_LC2_A3', type is buried
!_LC2_A3 = _LC2_A3~NOT;
_LC2_A3~NOT = LCELL( _EQ019);
_EQ019 = _LC1_A6 & _LC2_A6 & !_LC3_A6;
-- Node name is '|74138:12|:21' = '|74138:12|Y6N'
-- Equation name is '_LC8_A3', type is buried
!_LC8_A3 = _LC8_A3~NOT;
_LC8_A3~NOT = LCELL( _EQ020);
_EQ020 = !_LC1_A6 & _LC2_A6 & _LC3_A6;
Project Information e:\tt\tt\display\display.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:01
Memory Allocated
-----------------
Peak memory allocated during compilation = 12,892K
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