📄 my_83.rpt
字号:
- 5 - C 02 OR2 3 1 0 1 :467
- 1 - C 05 OR2 0 3 1 0 :548
- 2 - C 02 OR2 2 2 1 1 :554
- 8 - C 02 OR2 2 2 1 1 :560
- 7 - C 05 OR2 1 2 1 3 :566
- 4 - C 05 OR2 1 2 1 0 :572
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: d:\tt\8-3\my_83.rpt
my_83
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 2/ 96( 2%) 0/ 48( 0%) 0/ 48( 0%) 2/16( 12%) 0/16( 0%) 0/16( 0%)
C: 10/ 96( 10%) 6/ 48( 12%) 0/ 48( 0%) 5/16( 31%) 4/16( 25%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 2/24( 8%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\tt\8-3\my_83.rpt
my_83
** EQUATIONS **
d0 : INPUT;
d1 : INPUT;
d2 : INPUT;
d3 : INPUT;
d4 : INPUT;
d5 : INPUT;
d6 : INPUT;
d7 : INPUT;
Ein : INPUT;
-- Node name is 'Eon'
-- Equation name is 'Eon', type is output
Eon = _LC4_C5;
-- Node name is 'Gsn'
-- Equation name is 'Gsn', type is output
Gsn = _LC7_C5;
-- Node name is 'y0'
-- Equation name is 'y0', type is output
y0 = _LC8_C2;
-- Node name is 'y1'
-- Equation name is 'y1', type is output
y1 = _LC2_C2;
-- Node name is 'y2'
-- Equation name is 'y2', type is output
y2 = _LC1_C5;
-- Node name is '~175~1'
-- Equation name is '~175~1', location is LC1_C2, type is buried.
-- synthesized logic cell
!_LC1_C2 = _LC1_C2~NOT;
_LC1_C2~NOT = LCELL( _EQ001);
_EQ001 = d4 & d5 & d6 & d7;
-- Node name is '~175~2'
-- Equation name is '~175~2', location is LC3_C2, type is buried.
-- synthesized logic cell
_LC3_C2 = LCELL( _EQ002);
_EQ002 = !d3
# !d2
# !d1
# !d0;
-- Node name is '~381~1'
-- Equation name is '~381~1', location is LC1_C7, type is buried.
-- synthesized logic cell
!_LC1_C7 = _LC1_C7~NOT;
_LC1_C7~NOT = LCELL( _EQ003);
_EQ003 = d2 & d3;
-- Node name is ':420'
-- Equation name is '_LC6_C2', type is buried
_LC6_C2 = LCELL( _EQ004);
_EQ004 = _LC2_C2
# !d1
# !d0;
-- Node name is ':432'
-- Equation name is '_LC7_C2', type is buried
_LC7_C2 = LCELL( _EQ005);
_EQ005 = !d5
# !d4
# !_LC1_C7 & _LC6_C2;
-- Node name is ':453'
-- Equation name is '_LC4_C2', type is buried
_LC4_C2 = LCELL( _EQ006);
_EQ006 = !d2
# d1 & _LC8_C2
# !d0 & d1;
-- Node name is ':467'
-- Equation name is '_LC5_C2', type is buried
_LC5_C2 = LCELL( _EQ007);
_EQ007 = !d4 & d5
# d3 & d5 & _LC4_C2;
-- Node name is ':548'
-- Equation name is '_LC1_C5', type is buried
_LC1_C5 = LCELL( _EQ008);
_EQ008 = _LC7_C5
# !_LC1_C2 & _LC1_C5
# !_LC1_C2 & _LC3_C2;
-- Node name is ':554'
-- Equation name is '_LC2_C2', type is buried
_LC2_C2 = LCELL( _EQ009);
_EQ009 = _LC7_C5
# d6 & d7 & _LC7_C2;
-- Node name is ':560'
-- Equation name is '_LC8_C2', type is buried
_LC8_C2 = LCELL( _EQ010);
_EQ010 = _LC7_C5
# !d6 & d7
# d7 & _LC5_C2;
-- Node name is ':566'
-- Equation name is '_LC7_C5', type is buried
_LC7_C5 = LCELL( _EQ011);
_EQ011 = !_LC1_C2 & !_LC3_C2
# Ein;
-- Node name is ':572'
-- Equation name is '_LC4_C5', type is buried
_LC4_C5 = LCELL( _EQ012);
_EQ012 = _LC1_C2
# _LC3_C2
# Ein;
Project Information d:\tt\8-3\my_83.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:01
Memory Allocated
-----------------
Peak memory allocated during compilation = 13,422K
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