my_count4.vhd

大学vhdl语言实验大全,基于max-plus2平台,内有8-3译码器,8位加法器,数字钟

-- MAX+plus II 
-- Clearable my_count4

LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY my_count4 IS
PORT(res,clk	: IN	STD_LOGIC;
	 d	: OUT 	integer range 0 to 15);
END my_count4;

ARCHITECTURE behave OF my_count4 IS	
BEGIN
  P1:PROCESS(clk,res)
      variable data:integer range 0 to 15;
      variable ttt:integer range 0 to 15;
	BEGIN
     if(clk='0'and clk'event)then  
                      if(res='1' and data>=15)then data:=0;
                      elsif(res='1')then data:=data+1;  
                      end if;               
     end if;
      if(res='0')then 
      ttt:=0;
      data:=ttt;
      end if;
      d<=data;
     end PROCESS;
END behave;