📄 my_count4.rpt
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/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information:f:\maxplus_study\maxshiyan\my_count4\my_count4.rpt
my_count4
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 2 - A 13 OR2 ! 0 2 0 3 |LPM_ADD_SUB:61|addcore:adder|:59
- 5 - A 13 DFFE + 1 2 1 1 data3 (:7)
- 3 - A 13 DFFE + 1 1 1 2 data2 (:8)
- 1 - A 13 DFFE + 1 2 1 1 data1 (:9)
- 4 - A 13 DFFE + 1 0 1 2 data0 (:10)
- 6 - A 13 OR2 ! 1 3 0 1 :50
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information:f:\maxplus_study\maxshiyan\my_count4\my_count4.rpt
my_count4
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 5/ 48( 10%) 0/16( 0%) 4/16( 25%) 0/16( 0%)
B: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information:f:\maxplus_study\maxshiyan\my_count4\my_count4.rpt
my_count4
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 4 clk
Device-Specific Information:f:\maxplus_study\maxshiyan\my_count4\my_count4.rpt
my_count4
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 5 res
Device-Specific Information:f:\maxplus_study\maxshiyan\my_count4\my_count4.rpt
my_count4
** EQUATIONS **
clk : INPUT;
res : INPUT;
-- Node name is ':10' = 'data0'
-- Equation name is 'data0', location is LC4_A13, type is buried.
data0 = DFFE(!data0, GLOBAL(!clk), res, VCC, VCC);
-- Node name is ':9' = 'data1'
-- Equation name is 'data1', location is LC1_A13, type is buried.
data1 = DFFE( _EQ001, GLOBAL(!clk), res, VCC, VCC);
_EQ001 = !data0 & data1 & !_LC6_A13
# data0 & !data1 & !_LC6_A13;
-- Node name is ':8' = 'data2'
-- Equation name is 'data2', location is LC3_A13, type is buried.
data2 = DFFE( _EQ002, GLOBAL(!clk), res, VCC, VCC);
_EQ002 = data2 & !_LC2_A13
# !data2 & _LC2_A13;
-- Node name is ':7' = 'data3'
-- Equation name is 'data3', location is LC5_A13, type is buried.
data3 = DFFE( _EQ003, GLOBAL(!clk), res, VCC, VCC);
_EQ003 = !data2 & data3
# data3 & !_LC2_A13
# data2 & !data3 & _LC2_A13;
-- Node name is 'd0'
-- Equation name is 'd0', type is output
d0 = data0;
-- Node name is 'd1'
-- Equation name is 'd1', type is output
d1 = data1;
-- Node name is 'd2'
-- Equation name is 'd2', type is output
d2 = data2;
-- Node name is 'd3'
-- Equation name is 'd3', type is output
d3 = data3;
-- Node name is '|LPM_ADD_SUB:61|addcore:adder|:59' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC2_A13', type is buried
!_LC2_A13 = _LC2_A13~NOT;
_LC2_A13~NOT = LCELL( _EQ004);
_EQ004 = !data1
# !data0;
-- Node name is ':50'
-- Equation name is '_LC6_A13', type is buried
!_LC6_A13 = _LC6_A13~NOT;
_LC6_A13~NOT = LCELL( _EQ005);
_EQ005 = !data2
# !_LC2_A13
# !data3
# !res;
Project Information f:\maxplus_study\maxshiyan\my_count4\my_count4.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 13,290K
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