count60.vhd

来自「大学vhdl语言实验大全,基于max-plus2平台,内有8-3译码器,8位加法」· VHDL 代码 · 共 34 行

-- MAX+plus II 
-- Clearable count60

LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY count60 IS
	PORT(
		__input_name, __input_name		: IN	STD_LOGIC;
		__input_vector_name				: IN	STD_LOGIC_VECTOR(__high downto __low);
		__bidir_name, __bidir_name		: INOUT	STD_LOGIC;
		__output_name, __output_name	: OUT	STD_LOGIC);
END count60;

ARCHITECTURE a OF count60 IS
	SIGNAL __signal_name : STD_LOGIC;
	SIGNAL __signal_name : STD_LOGIC;
BEGIN
	--  Process Statement

	--  Concurrent Procedure Call

	--  Concurrent Signal Assignment

	--  Conditional Signal Assignment

	--  Selected Signal Assignment

	--  Component Instantiation Statement

	--  Generate Statement
END a;