choice6.vhd

大学vhdl语言实验大全,基于max-plus2平台,内有8-3译码器,8位加法器,数字钟

-- MAX+plus II 
-- Clearable choice6

LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY choice6 IS
	PORT(
		clk	,co	: IN	STD_LOGIC;
		a,b,c,d,e,f				: IN	STD_LOGIC_VECTOR(3 downto 0);
        da,db,dc,dd,de,df,dg   :out	STD_LOGIC;
        g				: out	STD_LOGIC_VECTOR(3 downto 0));
END choice6;

ARCHITECTURE a OF choice6 IS
	SIGNAL kk: STD_LOGIC_VECTOR(3 downto 0);
BEGIN
  process(clk)
   variable qqq : integer range 0 to 7;
  begin
   if(clk='1' and clk'event)then
     case qqq is 
        when 0=>kk<=a;da<='1';db<='0';dc<='0';dd<='0';de<='0';df<='0';dg<='0';
        when 1=>kk<=b;da<='0';db<='1';dc<='0';dd<='0';de<='0';df<='0';dg<='0';
        when 2=>kk<=c;da<='0';db<='0';dc<='1';dd<='0';de<='0';df<='0';dg<='0';
        when 3=>kk<=d;da<='0';db<='0';dc<='0';dd<='1';de<='0';df<='0';dg<='0';
        when 4=>da<='0';db<='0';dc<='0';dd<='0';de<='1';df<='0';dg<='0';
                if(co='1')then kk<="0001";
                else kk<="0000";
                end if;
        when 5=>kk<=e;da<='0';db<='0';dc<='0';dd<='0';de<='0';df<='1';dg<='0';
        when 6=>kk<=f;da<='0';db<='0';dc<='0';dd<='0';de<='0';df<='0';dg<='1';
        when others=>kk<=a;qqq:=0;da<='1';db<='0';dc<='0';dd<='0';de<='0';df<='0';dg<='0';
     end case;
    qqq:=qqq+1;
   end if;
   g<=kk;
 end process;
END a;