my_add8.vhd

大学vhdl语言实验大全,基于max-plus2平台,内有8-3译码器,8位加法器,数字钟

-- MAX+plus II 
-- Clearable my_add8

LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY my_add8 IS
	PORT(
		aa,ab,ba,bb				: IN	integer range 0 to 15;
        co              : out   STD_LOGIC;
		qa,qb				: out	integer range 0 to 15);
END my_add8;

ARCHITECTURE a OF my_add8 IS
 signal full:STD_LOGIC;
BEGIN
 process(aa,ab,ba,bb)
  variable ww : integer range 0 to 15;
  variable qq : integer range 0 to 15;
  variable jj : integer range 0 to 15;
  variable ll : integer range 0 to 15;
  variable eee : integer range 0 to 255;
  variable kkk : integer range 0 to 255;
 begin 
  ww:=aa;
  qq:=ab;
  jj:=ba;
  ll:=bb;
  eee:=ww+jj;
  kkk:=qq+ll;
  if(eee>15)then
    kkk:=kkk+1;
 end if;
  if(kkk>15)then 
    full<='1';
  else full<='0';
  end if;
 qa<=eee;
 qb<=kkk;
 co<=full;
end process;
END a;