📄 choice6.rpt
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-- Equation name is '_LC5_A19', type is buried
_LC5_A19 = DFFE( _EQ013, GLOBAL( clk), VCC, VCC, VCC);
_EQ013 = _LC8_A24 & qqq0 & !qqq1 & qqq2;
-- Node name is ':39'
-- Equation name is '_LC2_A23', type is buried
_LC2_A23 = DFFE( _EQ014, GLOBAL( clk), VCC, VCC, VCC);
_EQ014 = _LC3_A14 & !_LC3_A19 & !_LC3_A22 & !_LC6_A19;
-- Node name is ':442'
-- Equation name is '_LC3_A14', type is buried
_LC3_A14 = LCELL( _EQ015);
_EQ015 = !qqq0 & qqq1 & qqq2;
-- Node name is ':445'
-- Equation name is '_LC1_A24', type is buried
_LC1_A24 = LCELL( _EQ016);
_EQ016 = a3 & !_LC3_A14
# f3 & _LC3_A14;
-- Node name is ':452'
-- Equation name is '_LC3_A22', type is buried
!_LC3_A22 = _LC3_A22~NOT;
_LC3_A22~NOT = LCELL( _EQ017);
_EQ017 = !qqq2
# !qqq0
# qqq1;
-- Node name is ':455'
-- Equation name is '_LC3_A24', type is buried
_LC3_A24 = LCELL( _EQ018);
_EQ018 = _LC1_A24 & !_LC3_A22
# e3 & _LC3_A22;
-- Node name is ':462'
-- Equation name is '_LC3_A19', type is buried
_LC3_A19 = LCELL( _EQ019);
_EQ019 = !qqq0 & !qqq1 & qqq2;
-- Node name is ':472'
-- Equation name is '_LC6_A19', type is buried
!_LC6_A19 = _LC6_A19~NOT;
_LC6_A19~NOT = LCELL( _EQ020);
_EQ020 = !qqq0
# qqq2
# !qqq1;
-- Node name is ':475'
-- Equation name is '_LC4_A24', type is buried
_LC4_A24 = LCELL( _EQ021);
_EQ021 = _LC3_A24 & _LC8_A24
# d3 & _LC6_A19;
-- Node name is ':482'
-- Equation name is '_LC1_A22', type is buried
_LC1_A22 = LCELL( _EQ022);
_EQ022 = !qqq0 & qqq1 & !qqq2;
-- Node name is ':485'
-- Equation name is '_LC5_A24', type is buried
_LC5_A24 = LCELL( _EQ023);
_EQ023 = !_LC1_A22 & _LC4_A24
# c3 & _LC1_A22;
-- Node name is ':492'
-- Equation name is '_LC2_A22', type is buried
!_LC2_A22 = _LC2_A22~NOT;
_LC2_A22~NOT = LCELL( _EQ024);
_EQ024 = qqq2
# !qqq0
# qqq1;
-- Node name is ':495'
-- Equation name is '_LC6_A24', type is buried
_LC6_A24 = LCELL( _EQ025);
_EQ025 = !_LC2_A22 & _LC5_A24
# b3 & _LC2_A22;
-- Node name is ':502'
-- Equation name is '_LC4_A22', type is buried
_LC4_A22 = LCELL( _EQ026);
_EQ026 = !qqq0 & !qqq1 & !qqq2;
-- Node name is ':511'
-- Equation name is '_LC7_A19', type is buried
_LC7_A19 = LCELL( _EQ027);
_EQ027 = a2 & !_LC3_A14
# f2 & _LC3_A14;
-- Node name is ':514'
-- Equation name is '_LC8_A19', type is buried
_LC8_A19 = LCELL( _EQ028);
_EQ028 = !_LC3_A22 & _LC7_A19
# e2 & _LC3_A22;
-- Node name is ':520'
-- Equation name is '_LC2_A19', type is buried
_LC2_A19 = LCELL( _EQ029);
_EQ029 = _LC8_A19 & _LC8_A24
# d2 & _LC6_A19;
-- Node name is ':523'
-- Equation name is '_LC8_A16', type is buried
_LC8_A16 = LCELL( _EQ030);
_EQ030 = !_LC1_A22 & _LC2_A19
# c2 & _LC1_A22;
-- Node name is ':526'
-- Equation name is '_LC6_A16', type is buried
_LC6_A16 = LCELL( _EQ031);
_EQ031 = !_LC2_A22 & _LC8_A16
# b2 & _LC2_A22;
-- Node name is ':535'
-- Equation name is '_LC2_A16', type is buried
_LC2_A16 = LCELL( _EQ032);
_EQ032 = a1 & !_LC3_A14
# f1 & _LC3_A14;
-- Node name is ':538'
-- Equation name is '_LC3_A16', type is buried
_LC3_A16 = LCELL( _EQ033);
_EQ033 = _LC2_A16 & !_LC3_A22
# e1 & _LC3_A22;
-- Node name is ':544'
-- Equation name is '_LC4_A16', type is buried
_LC4_A16 = LCELL( _EQ034);
_EQ034 = _LC3_A16 & _LC8_A24
# d1 & _LC6_A19;
-- Node name is ':547'
-- Equation name is '_LC5_A16', type is buried
_LC5_A16 = LCELL( _EQ035);
_EQ035 = !_LC1_A22 & _LC4_A16
# c1 & _LC1_A22;
-- Node name is ':550'
-- Equation name is '_LC7_A16', type is buried
_LC7_A16 = LCELL( _EQ036);
_EQ036 = !_LC2_A22 & _LC5_A16
# b1 & _LC2_A22;
-- Node name is ':559'
-- Equation name is '_LC1_A23', type is buried
_LC1_A23 = LCELL( _EQ037);
_EQ037 = a0 & !_LC3_A14
# f0 & _LC3_A14;
-- Node name is ':562'
-- Equation name is '_LC3_A23', type is buried
_LC3_A23 = LCELL( _EQ038);
_EQ038 = _LC1_A23 & !_LC3_A22
# e0 & _LC3_A22;
-- Node name is ':565'
-- Equation name is '_LC4_A23', type is buried
_LC4_A23 = LCELL( _EQ039);
_EQ039 = !_LC3_A19 & _LC3_A23
# co & _LC3_A19;
-- Node name is ':568'
-- Equation name is '_LC5_A23', type is buried
_LC5_A23 = LCELL( _EQ040);
_EQ040 = _LC4_A23 & !_LC6_A19
# d0 & _LC6_A19;
-- Node name is ':571'
-- Equation name is '_LC6_A23', type is buried
_LC6_A23 = LCELL( _EQ041);
_EQ041 = !_LC1_A22 & _LC5_A23
# c0 & _LC1_A22;
-- Node name is ':574'
-- Equation name is '_LC8_A23', type is buried
_LC8_A23 = LCELL( _EQ042);
_EQ042 = !_LC2_A22 & _LC6_A23
# b0 & _LC2_A22;
-- Node name is '~723~1'
-- Equation name is '~723~1', location is LC8_A24, type is buried.
-- synthesized logic cell
_LC8_A24 = LCELL( _EQ043);
_EQ043 = !_LC3_A19 & !_LC6_A19;
-- Node name is ':808'
-- Equation name is '_LC8_A22', type is buried
!_LC8_A22 = _LC8_A22~NOT;
_LC8_A22~NOT = LCELL( _EQ044);
_EQ044 = !_LC3_A22 & !_LC6_A19;
Project Information f:\maxplus_study\tt\add8\choice6.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:01
Fitter 00:00:01
Timing SNF Extractor 00:00:01
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:03
Memory Allocated
-----------------
Peak memory allocated during compilation = 17,144K
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