📄 choice6.rpt
字号:
13 - - A -- OUTPUT 0 1 0 0 g0
7 - - A -- OUTPUT 0 1 0 0 g1
37 - - - 23 OUTPUT 0 1 0 0 g2
14 - - A -- OUTPUT 0 1 0 0 g3
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: f:\maxplus_study\tt\add8\choice6.rpt
choice6
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 1 - A 19 DFFE + 0 3 1 0 :27
- 6 - A 22 DFFE + 0 3 1 0 :29
- 1 - A 14 DFFE + 0 3 1 0 :31
- 8 - A 14 DFFE + 0 3 1 0 :33
- 4 - A 19 DFFE + 0 4 1 0 :35
- 5 - A 19 DFFE + 0 4 1 0 :37
- 2 - A 23 DFFE + 0 4 1 0 :39
- 7 - A 24 DFFE + 1 2 1 0 kk3 (:45)
- 2 - A 24 DFFE + 1 2 1 0 kk2 (:46)
- 1 - A 16 DFFE + 1 2 1 0 kk1 (:47)
- 7 - A 23 DFFE + 1 2 1 0 kk0 (:48)
- 7 - A 22 DFFE + 0 2 0 13 qqq2 (:49)
- 5 - A 14 DFFE + 0 1 0 14 qqq1 (:50)
- 5 - A 22 DFFE + 0 4 0 15 qqq0 (:51)
- 3 - A 14 AND2 0 3 0 5 :442
- 1 - A 24 OR2 2 1 0 1 :445
- 3 - A 22 OR2 ! 0 3 0 6 :452
- 3 - A 24 OR2 1 2 0 1 :455
- 3 - A 19 AND2 0 3 0 4 :462
- 6 - A 19 OR2 ! 0 3 0 7 :472
- 4 - A 24 OR2 1 3 0 1 :475
- 1 - A 22 AND2 0 3 0 5 :482
- 5 - A 24 OR2 1 2 0 1 :485
- 2 - A 22 OR2 ! 0 3 0 5 :492
- 6 - A 24 OR2 1 2 0 1 :495
- 4 - A 22 AND2 0 3 0 5 :502
- 7 - A 19 OR2 2 1 0 1 :511
- 8 - A 19 OR2 1 2 0 1 :514
- 2 - A 19 OR2 1 3 0 1 :520
- 8 - A 16 OR2 1 2 0 1 :523
- 6 - A 16 OR2 1 2 0 1 :526
- 2 - A 16 OR2 2 1 0 1 :535
- 3 - A 16 OR2 1 2 0 1 :538
- 4 - A 16 OR2 1 3 0 1 :544
- 5 - A 16 OR2 1 2 0 1 :547
- 7 - A 16 OR2 1 2 0 1 :550
- 1 - A 23 OR2 2 1 0 1 :559
- 3 - A 23 OR2 1 2 0 1 :562
- 4 - A 23 OR2 1 2 0 1 :565
- 5 - A 23 OR2 1 2 0 1 :568
- 6 - A 23 OR2 1 2 0 1 :571
- 8 - A 23 OR2 1 2 0 1 :574
- 8 - A 24 AND2 s 0 2 0 4 ~723~1
- 8 - A 22 AND2 ! 0 2 0 1 :808
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: f:\maxplus_study\tt\add8\choice6.rpt
choice6
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 17/ 96( 17%) 0/ 48( 0%) 27/ 48( 56%) 10/16( 62%) 6/16( 37%) 0/16( 0%)
B: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
14: 2/24( 8%) 1/4( 25%) 1/4( 25%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
17: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
18: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
19: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
20: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
21: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
24: 3/24( 12%) 3/4( 75%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: f:\maxplus_study\tt\add8\choice6.rpt
choice6
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 14 clk
Device-Specific Information: f:\maxplus_study\tt\add8\choice6.rpt
choice6
** EQUATIONS **
a0 : INPUT;
a1 : INPUT;
a2 : INPUT;
a3 : INPUT;
b0 : INPUT;
b1 : INPUT;
b2 : INPUT;
b3 : INPUT;
clk : INPUT;
co : INPUT;
c0 : INPUT;
c1 : INPUT;
c2 : INPUT;
c3 : INPUT;
d0 : INPUT;
d1 : INPUT;
d2 : INPUT;
d3 : INPUT;
e0 : INPUT;
e1 : INPUT;
e2 : INPUT;
e3 : INPUT;
f0 : INPUT;
f1 : INPUT;
f2 : INPUT;
f3 : INPUT;
-- Node name is 'da'
-- Equation name is 'da', type is output
da = _LC1_A19;
-- Node name is 'db'
-- Equation name is 'db', type is output
db = _LC6_A22;
-- Node name is 'dc'
-- Equation name is 'dc', type is output
dc = _LC1_A14;
-- Node name is 'dd'
-- Equation name is 'dd', type is output
dd = _LC8_A14;
-- Node name is 'de'
-- Equation name is 'de', type is output
de = _LC4_A19;
-- Node name is 'df'
-- Equation name is 'df', type is output
df = _LC5_A19;
-- Node name is 'dg'
-- Equation name is 'dg', type is output
dg = _LC2_A23;
-- Node name is 'g0'
-- Equation name is 'g0', type is output
g0 = kk0;
-- Node name is 'g1'
-- Equation name is 'g1', type is output
g1 = kk1;
-- Node name is 'g2'
-- Equation name is 'g2', type is output
g2 = kk2;
-- Node name is 'g3'
-- Equation name is 'g3', type is output
g3 = kk3;
-- Node name is ':48' = 'kk0'
-- Equation name is 'kk0', location is LC7_A23, type is buried.
kk0 = DFFE( _EQ001, GLOBAL( clk), VCC, VCC, VCC);
_EQ001 = !_LC4_A22 & _LC8_A23
# a0 & _LC4_A22;
-- Node name is ':47' = 'kk1'
-- Equation name is 'kk1', location is LC1_A16, type is buried.
kk1 = DFFE( _EQ002, GLOBAL( clk), VCC, VCC, VCC);
_EQ002 = !_LC4_A22 & _LC7_A16
# a1 & _LC4_A22;
-- Node name is ':46' = 'kk2'
-- Equation name is 'kk2', location is LC2_A24, type is buried.
kk2 = DFFE( _EQ003, GLOBAL( clk), VCC, VCC, VCC);
_EQ003 = !_LC4_A22 & _LC6_A16
# a2 & _LC4_A22;
-- Node name is ':45' = 'kk3'
-- Equation name is 'kk3', location is LC7_A24, type is buried.
kk3 = DFFE( _EQ004, GLOBAL( clk), VCC, VCC, VCC);
_EQ004 = !_LC4_A22 & _LC6_A24
# a3 & _LC4_A22;
-- Node name is ':51' = 'qqq0'
-- Equation name is 'qqq0', location is LC5_A22, type is buried.
qqq0 = DFFE( _EQ005, GLOBAL( clk), VCC, VCC, VCC);
_EQ005 = _LC4_A22
# _LC1_A22 & !_LC2_A22
# !_LC2_A22 & !_LC8_A22;
-- Node name is ':50' = 'qqq1'
-- Equation name is 'qqq1', location is LC5_A14, type is buried.
qqq1 = DFFE( _EQ006, GLOBAL( clk), VCC, VCC, VCC);
_EQ006 = !qqq0 & qqq1
# qqq0 & !qqq1;
-- Node name is ':49' = 'qqq2'
-- Equation name is 'qqq2', location is LC7_A22, type is buried.
qqq2 = DFFE( _EQ007, GLOBAL( clk), VCC, VCC, VCC);
_EQ007 = !qqq1 & qqq2
# !qqq0 & qqq2
# qqq0 & qqq1 & !qqq2;
-- Node name is ':27'
-- Equation name is '_LC1_A19', type is buried
_LC1_A19 = DFFE( _EQ008, GLOBAL( clk), VCC, VCC, VCC);
_EQ008 = !qqq0 & !qqq1 & !qqq2
# qqq0 & qqq1 & qqq2;
-- Node name is ':29'
-- Equation name is '_LC6_A22', type is buried
_LC6_A22 = DFFE( _EQ009, GLOBAL( clk), VCC, VCC, VCC);
_EQ009 = qqq0 & !qqq1 & !qqq2;
-- Node name is ':31'
-- Equation name is '_LC1_A14', type is buried
_LC1_A14 = DFFE( _EQ010, GLOBAL( clk), VCC, VCC, VCC);
_EQ010 = !qqq0 & qqq1 & !qqq2;
-- Node name is ':33'
-- Equation name is '_LC8_A14', type is buried
_LC8_A14 = DFFE( _EQ011, GLOBAL( clk), VCC, VCC, VCC);
_EQ011 = qqq0 & qqq1 & !qqq2;
-- Node name is ':35'
-- Equation name is '_LC4_A19', type is buried
_LC4_A19 = DFFE( _EQ012, GLOBAL( clk), VCC, VCC, VCC);
_EQ012 = _LC3_A19 & qqq2
# _LC3_A19 & !qqq1
# _LC3_A19 & !qqq0;
-- Node name is ':37'
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