📄 add8.rpt
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-- Equation name is '_LC2_B17', type is buried
_LC2_B17 = LCELL( _EQ046);
_EQ046 = d3 & _LC5_B23
# b3 & _LC5_B23
# b3 & d3;
-- Node name is '|MY_ADD8:27|LPM_ADD_SUB:106|addcore:adder|~79~1' from file "addcore.tdf" line 316, column 67
-- Equation name is '_LC5_B16', type is buried
-- synthesized logic cell
_LC5_B16 = LCELL( _EQ047);
_EQ047 = b0 & d0 & !d1
# !b0 & d1
# !d0 & d1;
-- Node name is '|MY_ADD8:27|LPM_ADD_SUB:106|addcore:adder|:80' from file "addcore.tdf" line 316, column 67
-- Equation name is '_LC1_B23', type is buried
_LC1_B23 = LCELL( _EQ048);
_EQ048 = b2 & d2 & _LC3_B16
# !b2 & !d2 & _LC3_B16
# !b2 & d2 & !_LC3_B16
# b2 & !d2 & !_LC3_B16;
-- Node name is '|MY_ADD8:27|LPM_ADD_SUB:106|addcore:adder|:81' from file "addcore.tdf" line 316, column 67
-- Equation name is '_LC3_B17', type is buried
_LC3_B17 = LCELL( _EQ049);
_EQ049 = !b3 & d3 & !_LC5_B23
# b3 & !d3 & !_LC5_B23
# b3 & d3 & _LC5_B23
# !b3 & !d3 & _LC5_B23;
-- Node name is '|MY_ADD8:27|LPM_ADD_SUB:115|addcore:adder|pcarry1' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC4_B24', type is buried
_LC4_B24 = LCELL( _EQ050);
_EQ050 = a1 & c1
# a0 & a1 & c0
# a0 & c0 & c1;
-- Node name is '|MY_ADD8:27|LPM_ADD_SUB:115|addcore:adder|pcarry2' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC4_B14', type is buried
_LC4_B14 = LCELL( _EQ051);
_EQ051 = c2 & _LC4_B24
# a2 & _LC4_B24
# a2 & c2;
-- Node name is '|MY_ADD8:27|LPM_ADD_SUB:115|addcore:adder|pcarry3' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC5_B14', type is buried
_LC5_B14 = LCELL( _EQ052);
_EQ052 = a3 & _LC4_B14
# c3 & _LC4_B14
# a3 & c3;
-- Node name is '|MY_ADD8:27|LPM_ADD_SUB:115|addcore:adder|:73' from file "addcore.tdf" line 315, column 26
-- Equation name is '_LC1_B18', type is buried
_LC1_B18 = LCELL( _EQ053);
_EQ053 = a0 & !c0
# !a0 & c0;
-- Node name is '|MY_ADD8:27|LPM_ADD_SUB:115|addcore:adder|:79' from file "addcore.tdf" line 316, column 67
-- Equation name is '_LC3_B24', type is buried
_LC3_B24 = LCELL( _EQ054);
_EQ054 = a0 & a1 & c0 & c1
# !a0 & a1 & !c1
# a1 & !c0 & !c1
# !a0 & !a1 & c1
# !a1 & !c0 & c1
# a0 & !a1 & c0 & !c1;
-- Node name is '|MY_ADD8:27|LPM_ADD_SUB:115|addcore:adder|:80' from file "addcore.tdf" line 316, column 67
-- Equation name is '_LC6_B14', type is buried
_LC6_B14 = LCELL( _EQ055);
_EQ055 = a2 & c2 & _LC4_B24
# !a2 & !c2 & _LC4_B24
# !a2 & c2 & !_LC4_B24
# a2 & !c2 & !_LC4_B24;
-- Node name is '|MY_ADD8:27|LPM_ADD_SUB:115|addcore:adder|:81' from file "addcore.tdf" line 316, column 67
-- Equation name is '_LC8_B14', type is buried
_LC8_B14 = LCELL( _EQ056);
_EQ056 = a3 & !c3 & !_LC4_B14
# !a3 & c3 & !_LC4_B14
# a3 & c3 & _LC4_B14
# !a3 & !c3 & _LC4_B14;
-- Node name is '|MY_ADD8:27|LPM_ADD_SUB:178|addcore:adder|:75' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC6_B24', type is buried
_LC6_B24 = LCELL( _EQ057);
_EQ057 = _LC1_B18 & _LC3_B24;
-- Node name is '|MY_ADD8:27|LPM_ADD_SUB:178|addcore:adder|:79' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC7_B14', type is buried
_LC7_B14 = LCELL( _EQ058);
_EQ058 = _LC6_B14 & _LC6_B24;
-- Node name is '|MY_ADD8:27|:220'
-- Equation name is '_LC2_B14', type is buried
_LC2_B14 = LCELL( _EQ059);
_EQ059 = !_LC2_B17 & _LC8_B14
# _LC2_B17 & _LC6_B14 & _LC6_B24 & !_LC8_B14
# !_LC6_B14 & _LC8_B14
# !_LC6_B24 & _LC8_B14;
-- Node name is '|MY_ADD8:27|:226'
-- Equation name is '_LC1_B14', type is buried
_LC1_B14 = LCELL( _EQ060);
_EQ060 = !_LC2_B17 & _LC6_B14
# _LC6_B14 & !_LC6_B24
# _LC2_B17 & !_LC6_B14 & _LC6_B24;
-- Node name is '|MY_ADD8:27|:232'
-- Equation name is '_LC2_B16', type is buried
_LC2_B16 = LCELL( _EQ061);
_EQ061 = !_LC2_B17 & _LC3_B24
# !_LC1_B18 & _LC3_B24
# _LC1_B18 & _LC2_B17 & !_LC3_B24;
-- Node name is '|MY_ADD8:27|:251'
-- Equation name is '_LC3_B14', type is buried
_LC3_B14 = LCELL( _EQ062);
_EQ062 = _LC5_B14
# _LC2_B17 & _LC7_B14 & _LC8_B14;
-- Node name is '|7448:24|:69' = '|7448:24|OA'
-- Equation name is '_LC3_B10', type is buried
_LC3_B10 = LCELL( _EQ063);
_EQ063 = _LC1_B17 & !_LC1_B24 & _LC6_B10
# _LC1_B17 & !_LC1_B24 & !_LC2_B23
# !_LC1_B17 & !_LC2_B23 & !_LC6_B10
# !_LC1_B24 & !_LC2_B23 & !_LC6_B10
# !_LC1_B17 & _LC1_B24 & _LC6_B10
# !_LC1_B17 & _LC1_B24 & !_LC2_B23
# !_LC1_B17 & _LC2_B23 & _LC6_B10
# !_LC1_B24 & _LC2_B23 & _LC6_B10;
-- Node name is '|7448:24|:68' = '|7448:24|OB'
-- Equation name is '_LC8_B10', type is buried
_LC8_B10 = LCELL( _EQ064);
_EQ064 = !_LC1_B24 & !_LC6_B10
# !_LC1_B17 & _LC1_B24 & _LC6_B10
# !_LC1_B17 & !_LC2_B23
# !_LC1_B24 & !_LC2_B23;
-- Node name is '|7448:24|:70' = '|7448:24|OC'
-- Equation name is '_LC7_B10', type is buried
_LC7_B10 = LCELL( _EQ065);
_EQ065 = !_LC1_B17 & _LC6_B10
# !_LC2_B23 & _LC6_B10
# !_LC1_B17 & !_LC1_B24
# !_LC1_B24 & !_LC2_B23
# !_LC1_B17 & _LC2_B23;
-- Node name is '|7448:24|:67' = '|7448:24|OD'
-- Equation name is '_LC1_B10', type is buried
_LC1_B10 = LCELL( _EQ066);
_EQ066 = _LC1_B24 & !_LC6_B10
# _LC1_B24 & !_LC2_B23
# !_LC1_B24 & _LC2_B23 & _LC6_B10
# !_LC2_B23 & !_LC6_B10;
-- Node name is '|7448:24|:71' = '|7448:24|OE'
-- Equation name is '_LC2_B10', type is buried
_LC2_B10 = LCELL( _EQ067);
_EQ067 = _LC1_B24 & !_LC6_B10
# !_LC2_B23 & !_LC6_B10;
-- Node name is '|7448:24|:66' = '|7448:24|OF'
-- Equation name is '_LC4_B10', type is buried
_LC4_B10 = LCELL( _EQ068);
_EQ068 = _LC1_B17 & !_LC1_B24
# !_LC1_B24 & !_LC6_B10
# _LC2_B23 & !_LC6_B10
# !_LC1_B24 & _LC2_B23;
-- Node name is '|7448:24|:72' = '|7448:24|OG'
-- Equation name is '_LC5_B10', type is buried
_LC5_B10 = LCELL( _EQ069);
_EQ069 = _LC1_B24 & !_LC6_B10
# _LC1_B24 & !_LC2_B23
# _LC2_B23 & !_LC6_B10
# !_LC1_B24 & _LC2_B23
# _LC1_B17 & !_LC6_B10
# _LC1_B17 & !_LC1_B24
# _LC1_B17 & !_LC2_B23;
Project Information f:\maxplus_study\tt\add8\add8.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:01
Fitter 00:00:02
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:03
Memory Allocated
-----------------
Peak memory allocated during compilation = 17,309K
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