📄 add8.rpt
字号:
73 - - A -- INPUT 0 0 0 3 d2
72 - - A -- INPUT 0 0 0 3 d3
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: f:\maxplus_study\tt\add8\add8.rpt
add8
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
17 - - A -- OUTPUT 0 1 0 0 a
18 - - A -- OUTPUT 0 1 0 0 b
19 - - A -- OUTPUT 0 1 0 0 c
21 - - B -- OUTPUT 0 1 0 0 d
16 - - A -- OUTPUT 0 1 0 0 da
9 - - - 02 OUTPUT 0 1 0 0 db
29 - - C -- OUTPUT 0 1 0 0 dc
28 - - C -- OUTPUT 0 1 0 0 dd
25 - - B -- OUTPUT 0 1 0 0 de
11 - - - 01 OUTPUT 0 1 0 0 df
10 - - - 01 OUTPUT 0 1 0 0 dg
22 - - B -- OUTPUT 0 1 0 0 e
23 - - B -- OUTPUT 0 1 0 0 f
24 - - B -- OUTPUT 0 1 0 0 g
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: f:\maxplus_study\tt\add8\add8.rpt
add8
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 1 - B 02 DFFE + 0 3 1 0 |CHOICE6:44|:27
- 7 - B 02 DFFE + 0 3 1 0 |CHOICE6:44|:29
- 5 - B 02 DFFE + 0 3 1 0 |CHOICE6:44|:31
- 3 - B 02 DFFE + 0 3 1 0 |CHOICE6:44|:33
- 8 - B 02 DFFE + 0 3 1 0 |CHOICE6:44|:35
- 6 - B 02 DFFE + 0 3 1 0 |CHOICE6:44|:37
- 4 - B 02 DFFE + 0 3 1 0 |CHOICE6:44|:39
- 1 - B 17 DFFE + 1 2 0 5 |CHOICE6:44|kk3 (|CHOICE6:44|:45)
- 2 - B 23 DFFE + 1 2 0 7 |CHOICE6:44|kk2 (|CHOICE6:44|:46)
- 1 - B 24 DFFE + 1 2 0 7 |CHOICE6:44|kk1 (|CHOICE6:44|:47)
- 6 - B 10 DFFE + 1 2 0 7 |CHOICE6:44|kk0 (|CHOICE6:44|:48)
- 2 - B 02 DFFE + 0 2 0 14 |CHOICE6:44|qqq2 (|CHOICE6:44|:49)
- 2 - B 15 DFFE + 0 1 0 15 |CHOICE6:44|qqq1 (|CHOICE6:44|:50)
- 1 - B 15 DFFE + 0 3 0 16 |CHOICE6:44|qqq0 (|CHOICE6:44|:51)
- 1 - B 16 OR2 ! 0 3 0 4 |CHOICE6:44|:442
- 4 - B 17 OR2 1 2 0 1 |CHOICE6:44|:445
- 4 - B 15 OR2 ! 0 3 0 5 |CHOICE6:44|:452
- 5 - B 17 OR2 0 3 0 1 |CHOICE6:44|:455
- 6 - B 16 OR2 ! 0 3 0 4 |CHOICE6:44|:462
- 3 - B 15 OR2 ! 0 3 0 5 |CHOICE6:44|:472
- 6 - B 17 OR2 1 3 0 1 |CHOICE6:44|:475
- 6 - B 15 AND2 0 3 0 5 |CHOICE6:44|:482
- 7 - B 17 OR2 1 2 0 1 |CHOICE6:44|:485
- 8 - B 15 OR2 ! 0 3 0 5 |CHOICE6:44|:492
- 8 - B 17 OR2 1 2 0 1 |CHOICE6:44|:495
- 5 - B 15 AND2 0 3 0 5 |CHOICE6:44|:502
- 3 - B 23 OR2 1 2 0 1 |CHOICE6:44|:511
- 4 - B 23 OR2 0 3 0 1 |CHOICE6:44|:514
- 6 - B 23 OR2 1 3 0 1 |CHOICE6:44|:520
- 7 - B 23 OR2 1 2 0 1 |CHOICE6:44|:523
- 8 - B 23 OR2 1 2 0 1 |CHOICE6:44|:526
- 7 - B 16 OR2 2 2 0 1 |CHOICE6:44|:535
- 8 - B 16 OR2 0 3 0 1 |CHOICE6:44|:538
- 4 - B 16 OR2 1 3 0 1 |CHOICE6:44|:544
- 2 - B 24 OR2 1 2 0 1 |CHOICE6:44|:547
- 5 - B 24 OR2 1 2 0 1 |CHOICE6:44|:550
- 3 - B 18 OR2 3 1 0 1 |CHOICE6:44|:559
- 4 - B 18 OR2 0 4 0 1 |CHOICE6:44|:562
- 5 - B 18 OR2 0 3 0 1 |CHOICE6:44|:565
- 6 - B 18 OR2 1 2 0 1 |CHOICE6:44|:568
- 7 - B 18 OR2 1 2 0 1 |CHOICE6:44|:571
- 2 - B 18 OR2 1 2 0 1 |CHOICE6:44|:574
- 7 - B 15 OR2 ! 0 3 0 1 |CHOICE6:44|:813
- 3 - B 16 OR2 4 0 0 2 |MY_ADD8:27|LPM_ADD_SUB:106|addcore:adder|pcarry1
- 5 - B 23 OR2 2 1 0 2 |MY_ADD8:27|LPM_ADD_SUB:106|addcore:adder|pcarry2
- 2 - B 17 OR2 2 1 0 5 |MY_ADD8:27|LPM_ADD_SUB:106|addcore:adder|pcarry3
- 5 - B 16 OR2 s 3 0 0 1 |MY_ADD8:27|LPM_ADD_SUB:106|addcore:adder|~79~1
- 1 - B 23 OR2 2 1 0 1 |MY_ADD8:27|LPM_ADD_SUB:106|addcore:adder|:80
- 3 - B 17 OR2 2 1 0 1 |MY_ADD8:27|LPM_ADD_SUB:106|addcore:adder|:81
- 4 - B 24 OR2 4 0 0 2 |MY_ADD8:27|LPM_ADD_SUB:115|addcore:adder|pcarry1
- 4 - B 14 OR2 2 1 0 2 |MY_ADD8:27|LPM_ADD_SUB:115|addcore:adder|pcarry2
- 5 - B 14 OR2 2 1 0 1 |MY_ADD8:27|LPM_ADD_SUB:115|addcore:adder|pcarry3
- 1 - B 18 OR2 2 0 0 3 |MY_ADD8:27|LPM_ADD_SUB:115|addcore:adder|:73
- 3 - B 24 OR2 4 0 0 2 |MY_ADD8:27|LPM_ADD_SUB:115|addcore:adder|:79
- 6 - B 14 OR2 2 1 0 3 |MY_ADD8:27|LPM_ADD_SUB:115|addcore:adder|:80
- 8 - B 14 OR2 2 1 0 2 |MY_ADD8:27|LPM_ADD_SUB:115|addcore:adder|:81
- 6 - B 24 AND2 0 2 0 3 |MY_ADD8:27|LPM_ADD_SUB:178|addcore:adder|:75
- 7 - B 14 AND2 0 2 0 1 |MY_ADD8:27|LPM_ADD_SUB:178|addcore:adder|:79
- 2 - B 14 OR2 0 4 0 1 |MY_ADD8:27|:220
- 1 - B 14 OR2 0 3 0 1 |MY_ADD8:27|:226
- 2 - B 16 OR2 0 3 0 1 |MY_ADD8:27|:232
- 3 - B 14 OR2 0 4 0 1 |MY_ADD8:27|:251
- 4 - B 10 OR2 0 4 1 0 |7448:24|OF (|7448:24|:66)
- 1 - B 10 OR2 0 3 1 0 |7448:24|OD (|7448:24|:67)
- 8 - B 10 OR2 0 4 1 0 |7448:24|OB (|7448:24|:68)
- 3 - B 10 OR2 0 4 1 0 |7448:24|OA (|7448:24|:69)
- 7 - B 10 OR2 0 4 1 0 |7448:24|OC (|7448:24|:70)
- 2 - B 10 OR2 0 3 1 0 |7448:24|OE (|7448:24|:71)
- 5 - B 10 OR2 0 4 1 0 |7448:24|OG (|7448:24|:72)
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: f:\maxplus_study\tt\add8\add8.rpt
add8
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 4/ 96( 4%) 4/ 48( 8%) 0/ 48( 0%) 4/16( 25%) 4/16( 25%) 0/16( 0%)
B: 20/ 96( 20%) 5/ 48( 10%) 24/ 48( 50%) 4/16( 25%) 5/16( 31%) 0/16( 0%)
C: 5/ 96( 5%) 2/ 48( 4%) 0/ 48( 0%) 5/16( 31%) 2/16( 12%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
02: 4/24( 16%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 2/24( 8%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
22: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 4/24( 16%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: f:\maxplus_study\tt\add8\add8.rpt
add8
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 14 clk
Device-Specific Information: f:\maxplus_study\tt\add8\add8.rpt
add8
** EQUATIONS **
a0 : INPUT;
a1 : INPUT;
a2 : INPUT;
a3 : INPUT;
b0 : INPUT;
b1 : INPUT;
b2 : INPUT;
b3 : INPUT;
clk : INPUT;
c0 : INPUT;
c1 : INPUT;
c2 : INPUT;
c3 : INPUT;
d0 : INPUT;
d1 : INPUT;
d2 : INPUT;
d3 : INPUT;
-- Node name is 'a'
-- Equation name is 'a', type is output
a = _LC3_B10;
-- Node name is 'b'
-- Equation name is 'b', type is output
b = _LC8_B10;
-- Node name is 'c'
-- Equation name is 'c', type is output
c = _LC7_B10;
-- Node name is 'd'
-- Equation name is 'd', type is output
d = _LC1_B10;
-- Node name is 'da'
-- Equation name is 'da', type is output
da = _LC1_B2;
-- Node name is 'db'
-- Equation name is 'db', type is output
db = _LC7_B2;
-- Node name is 'dc'
-- Equation name is 'dc', type is output
dc = _LC5_B2;
-- Node name is 'dd'
-- Equation name is 'dd', type is output
dd = _LC3_B2;
-- Node name is 'de'
-- Equation name is 'de', type is output
de = _LC8_B2;
-- Node name is 'df'
-- Equation name is 'df', type is output
df = _LC6_B2;
-- Node name is 'dg'
-- Equation name is 'dg', type is output
dg = _LC4_B2;
-- Node name is 'e'
-- Equation name is 'e', type is output
e = _LC2_B10;
-- Node name is 'f'
-- Equation name is 'f', type is output
f = _LC4_B10;
-- Node name is 'g'
-- Equation name is 'g', type is output
g = _LC5_B10;
-- Node name is '|CHOICE6:44|:48' = '|CHOICE6:44|kk0'
-- Equation name is '_LC6_B10', type is buried
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