colordisplay.vhd

大学vhdl语言实验大全,基于max-plus2平台,内有8-3译码器,8位加法器,数字钟

-- MAX+plus II 
-- Clearable colordisplay

LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY colordisplay IS
	PORT(
		clk		: IN	STD_LOGIC;
		d				: buffer	STD_LOGIC_VECTOR(5 downto 0));
END colordisplay;

ARCHITECTURE a OF colordisplay IS
BEGIN
  process(clk)
   variable kkk : integer range 0 to 255;
  begin
   if(clk='1' and clk'event)then
     case kkk is
        when 0 =>d<="000000";
        when 1 =>d<="001100";
        when 2 =>d<="011110";
        when 3 =>d<="111111";
        when 4 =>d<="011110";
        when 5 =>d<="001100";
        when 6 =>d<="000000";
        when 7 =>d<="100000";
        when 8 =>d<="010000";
        when 9 =>d<="001000";
        when 10 =>d<="000100";
        when 11 =>d<="000010";
        when 12 =>d<="000001";
        when 13 =>d<="000010";
        when 14 =>d<="000100";
        when 15 =>d<="001000";
        when 16 =>d<="010000";
        when 17 =>d<="100000";kkk:=0;
        when others=>kkk:=0;
      end case;
    end if;
    kkk:=kkk+1;
end process;
END a;