choice6.rpt

大学vhdl语言实验大全,基于max-plus2平台,内有8-3译码器,8位加法器,数字钟

-- Node name is ':36' 
-- Equation name is '_LC1_A16', type is buried 
_LC1_A16 = DFFE( _EQ013, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ013 = !_LC1_A15 & !_LC4_A13 &  _LC5_A15;

-- Node name is ':350' 
-- Equation name is '_LC5_A15', type is buried 
!_LC5_A15 = _LC5_A15~NOT;
_LC5_A15~NOT = LCELL( _EQ014);
  _EQ014 = !qqq2
         # !qqq0
         #  qqq1;

-- Node name is ':353' 
-- Equation name is '_LC2_A16', type is buried 
_LC2_A16 = LCELL( _EQ015);
  _EQ015 =  a3 & !_LC5_A15
         #  f3 &  _LC5_A15;

-- Node name is ':360' 
-- Equation name is '_LC1_A15', type is buried 
_LC1_A15 = LCELL( _EQ016);
  _EQ016 = !qqq0 & !qqq1 &  qqq2;

-- Node name is ':363' 
-- Equation name is '_LC3_A16', type is buried 
_LC3_A16 = LCELL( _EQ017);
  _EQ017 = !_LC1_A15 &  _LC2_A16
         #  e3 &  _LC1_A15;

-- Node name is ':370' 
-- Equation name is '_LC4_A13', type is buried 
!_LC4_A13 = _LC4_A13~NOT;
_LC4_A13~NOT = LCELL( _EQ018);
  _EQ018 = !qqq0
         #  qqq2
         # !qqq1;

-- Node name is ':373' 
-- Equation name is '_LC4_A16', type is buried 
_LC4_A16 = LCELL( _EQ019);
  _EQ019 =  _LC3_A16 & !_LC4_A13
         #  d3 &  _LC4_A13;

-- Node name is ':380' 
-- Equation name is '_LC2_A13', type is buried 
_LC2_A13 = LCELL( _EQ020);
  _EQ020 = !qqq0 &  qqq1 & !qqq2;

-- Node name is ':383' 
-- Equation name is '_LC5_A16', type is buried 
_LC5_A16 = LCELL( _EQ021);
  _EQ021 = !_LC2_A13 &  _LC4_A16
         #  c3 &  _LC2_A13;

-- Node name is ':390' 
-- Equation name is '_LC6_A13', type is buried 
!_LC6_A13 = _LC6_A13~NOT;
_LC6_A13~NOT = LCELL( _EQ022);
  _EQ022 =  qqq2
         # !qqq0
         #  qqq1;

-- Node name is ':393' 
-- Equation name is '_LC7_A16', type is buried 
_LC7_A16 = LCELL( _EQ023);
  _EQ023 =  _LC5_A16 & !_LC6_A13
         #  b3 &  _LC6_A13;

-- Node name is ':400' 
-- Equation name is '_LC8_A24', type is buried 
_LC8_A24 = LCELL( _EQ024);
  _EQ024 = !qqq0 & !qqq1 & !qqq2;

-- Node name is ':409' 
-- Equation name is '_LC3_A24', type is buried 
_LC3_A24 = LCELL( _EQ025);
  _EQ025 =  a2 & !_LC5_A15
         #  f2 &  _LC5_A15;

-- Node name is ':412' 
-- Equation name is '_LC4_A24', type is buried 
_LC4_A24 = LCELL( _EQ026);
  _EQ026 = !_LC1_A15 &  _LC3_A24
         #  e2 &  _LC1_A15;

-- Node name is ':415' 
-- Equation name is '_LC5_A24', type is buried 
_LC5_A24 = LCELL( _EQ027);
  _EQ027 = !_LC4_A13 &  _LC4_A24
         #  d2 &  _LC4_A13;

-- Node name is ':418' 
-- Equation name is '_LC6_A24', type is buried 
_LC6_A24 = LCELL( _EQ028);
  _EQ028 = !_LC2_A13 &  _LC5_A24
         #  c2 &  _LC2_A13;

-- Node name is ':421' 
-- Equation name is '_LC7_A24', type is buried 
_LC7_A24 = LCELL( _EQ029);
  _EQ029 = !_LC6_A13 &  _LC6_A24
         #  b2 &  _LC6_A13;

-- Node name is ':430' 
-- Equation name is '_LC3_A19', type is buried 
_LC3_A19 = LCELL( _EQ030);
  _EQ030 =  a1 & !_LC5_A15
         #  f1 &  _LC5_A15;

-- Node name is ':433' 
-- Equation name is '_LC4_A19', type is buried 
_LC4_A19 = LCELL( _EQ031);
  _EQ031 = !_LC1_A15 &  _LC3_A19
         #  e1 &  _LC1_A15;

-- Node name is ':436' 
-- Equation name is '_LC5_A19', type is buried 
_LC5_A19 = LCELL( _EQ032);
  _EQ032 = !_LC4_A13 &  _LC4_A19
         #  d1 &  _LC4_A13;

-- Node name is ':439' 
-- Equation name is '_LC7_A19', type is buried 
_LC7_A19 = LCELL( _EQ033);
  _EQ033 = !_LC2_A13 &  _LC5_A19
         #  c1 &  _LC2_A13;

-- Node name is ':442' 
-- Equation name is '_LC8_A19', type is buried 
_LC8_A19 = LCELL( _EQ034);
  _EQ034 = !_LC6_A13 &  _LC7_A19
         #  b1 &  _LC6_A13;

-- Node name is ':451' 
-- Equation name is '_LC2_A14', type is buried 
_LC2_A14 = LCELL( _EQ035);
  _EQ035 =  a0 & !_LC5_A15
         #  f0 &  _LC5_A15;

-- Node name is ':454' 
-- Equation name is '_LC4_A14', type is buried 
_LC4_A14 = LCELL( _EQ036);
  _EQ036 = !_LC1_A15 &  _LC2_A14
         #  e0 &  _LC1_A15;

-- Node name is ':457' 
-- Equation name is '_LC5_A14', type is buried 
_LC5_A14 = LCELL( _EQ037);
  _EQ037 = !_LC4_A13 &  _LC4_A14
         #  d0 &  _LC4_A13;

-- Node name is ':460' 
-- Equation name is '_LC6_A14', type is buried 
_LC6_A14 = LCELL( _EQ038);
  _EQ038 = !_LC2_A13 &  _LC5_A14
         #  c0 &  _LC2_A13;

-- Node name is ':463' 
-- Equation name is '_LC7_A14', type is buried 
_LC7_A14 = LCELL( _EQ039);
  _EQ039 = !_LC6_A13 &  _LC6_A14
         #  b0 &  _LC6_A13;

-- Node name is ':652' 
-- Equation name is '_LC2_A19', type is buried 
!_LC2_A19 = _LC2_A19~NOT;
_LC2_A19~NOT = LCELL( _EQ040);
  _EQ040 = !_LC4_A13 & !_LC5_A15 & !_LC6_A13
         #  _LC2_A13 & !_LC6_A13;

-- Node name is '~767~1' 
-- Equation name is '~767~1', location is LC1_A24, type is buried.
-- synthesized logic cell 
_LC1_A24 = LCELL( _EQ041);
  _EQ041 = !c2 & !d2 & !d3;

-- Node name is '~767~2' 
-- Equation name is '~767~2', location is LC8_A14, type is buried.
-- synthesized logic cell 
_LC8_A14 = LCELL( _EQ042);
  _EQ042 = !c0 & !d0 & !d1;

-- Node name is ':767' 
-- Equation name is '_LC3_A14', type is buried 
_LC3_A14 = LCELL( _EQ043);
  _EQ043 = !c1 & !c3 &  _LC1_A24 &  _LC8_A14;



Project Information                    f:\maxplus_study\tt\choice6\choice6.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'FLEX10K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:01
   Fitter                                 00:00:01
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:01
   --------------------------             --------
   Total Time                             00:00:03


Memory Allocated
-----------------

Peak memory allocated during compilation  = 17,613K