📄 choice6.rpt
字号:
131 - - - 15 OUTPUT 0 1 0 0 df
7 - - A -- OUTPUT 0 1 0 0 g0
12 - - A -- OUTPUT 0 1 0 0 g1
36 - - - 24 OUTPUT 0 1 0 0 g2
132 - - - 16 OUTPUT 0 1 0 0 g3
130 - - - 14 OUTPUT 0 1 0 0 speak
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: f:\maxplus_study\tt\choice6\choice6.rpt
choice6
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 7 - A 15 DFFE + 0 3 1 0 :26
- 5 - A 13 DFFE + 0 3 1 0 :28
- 2 - A 15 DFFE + 0 3 1 0 :30
- 4 - A 15 DFFE + 0 3 1 0 :32
- 3 - A 15 DFFE + 0 4 1 0 :34
- 1 - A 16 DFFE + 0 3 1 0 :36
- 6 - A 16 DFFE + 1 2 1 0 kk3 (:43)
- 2 - A 24 DFFE + 1 2 1 0 kk2 (:44)
- 6 - A 19 DFFE + 1 2 1 0 kk1 (:45)
- 1 - A 14 DFFE + 1 2 1 0 kk0 (:46)
- 6 - A 15 DFFE + 0 2 0 12 qqq2 (:47)
- 8 - A 15 DFFE + 0 2 0 12 qqq1 (:48)
- 1 - A 19 DFFE + 0 2 0 13 qqq0 (:49)
- 5 - A 15 OR2 ! 0 3 0 6 :350
- 2 - A 16 OR2 2 1 0 1 :353
- 1 - A 15 AND2 0 3 0 6 :360
- 3 - A 16 OR2 1 2 0 1 :363
- 4 - A 13 OR2 ! 0 3 0 6 :370
- 4 - A 16 OR2 1 2 0 1 :373
- 2 - A 13 AND2 0 3 0 5 :380
- 5 - A 16 OR2 1 2 0 1 :383
- 6 - A 13 OR2 ! 0 3 0 5 :390
- 7 - A 16 OR2 1 2 0 1 :393
- 8 - A 24 AND2 0 3 0 5 :400
- 3 - A 24 OR2 2 1 0 1 :409
- 4 - A 24 OR2 1 2 0 1 :412
- 5 - A 24 OR2 1 2 0 1 :415
- 6 - A 24 OR2 1 2 0 1 :418
- 7 - A 24 OR2 1 2 0 1 :421
- 3 - A 19 OR2 2 1 0 1 :430
- 4 - A 19 OR2 1 2 0 1 :433
- 5 - A 19 OR2 1 2 0 1 :436
- 7 - A 19 OR2 1 2 0 1 :439
- 8 - A 19 OR2 1 2 0 1 :442
- 2 - A 14 OR2 2 1 0 1 :451
- 4 - A 14 OR2 1 2 0 1 :454
- 5 - A 14 OR2 1 2 0 1 :457
- 6 - A 14 OR2 1 2 0 1 :460
- 7 - A 14 OR2 1 2 0 1 :463
- 2 - A 19 OR2 ! 0 4 0 1 :652
- 1 - A 24 AND2 s 3 0 0 1 ~767~1
- 8 - A 14 AND2 s 3 0 0 1 ~767~2
- 3 - A 14 AND2 2 2 1 0 :767
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: f:\maxplus_study\tt\choice6\choice6.rpt
choice6
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 18/ 96( 18%) 0/ 48( 0%) 19/ 48( 39%) 10/16( 62%) 6/16( 37%) 0/16( 0%)
B: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
14: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
15: 2/24( 8%) 1/4( 25%) 1/4( 25%) 0/4( 0%)
16: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
17: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
18: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
19: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
20: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 3/24( 12%) 2/4( 50%) 1/4( 25%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: f:\maxplus_study\tt\choice6\choice6.rpt
choice6
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 13 clk
Device-Specific Information: f:\maxplus_study\tt\choice6\choice6.rpt
choice6
** EQUATIONS **
a0 : INPUT;
a1 : INPUT;
a2 : INPUT;
a3 : INPUT;
b0 : INPUT;
b1 : INPUT;
b2 : INPUT;
b3 : INPUT;
clk : INPUT;
c0 : INPUT;
c1 : INPUT;
c2 : INPUT;
c3 : INPUT;
d0 : INPUT;
d1 : INPUT;
d2 : INPUT;
d3 : INPUT;
e0 : INPUT;
e1 : INPUT;
e2 : INPUT;
e3 : INPUT;
f0 : INPUT;
f1 : INPUT;
f2 : INPUT;
f3 : INPUT;
-- Node name is 'da'
-- Equation name is 'da', type is output
da = _LC7_A15;
-- Node name is 'db'
-- Equation name is 'db', type is output
db = _LC5_A13;
-- Node name is 'dc'
-- Equation name is 'dc', type is output
dc = _LC2_A15;
-- Node name is 'dd'
-- Equation name is 'dd', type is output
dd = _LC4_A15;
-- Node name is 'de'
-- Equation name is 'de', type is output
de = _LC3_A15;
-- Node name is 'df'
-- Equation name is 'df', type is output
df = _LC1_A16;
-- Node name is 'g0'
-- Equation name is 'g0', type is output
g0 = kk0;
-- Node name is 'g1'
-- Equation name is 'g1', type is output
g1 = kk1;
-- Node name is 'g2'
-- Equation name is 'g2', type is output
g2 = kk2;
-- Node name is 'g3'
-- Equation name is 'g3', type is output
g3 = kk3;
-- Node name is ':46' = 'kk0'
-- Equation name is 'kk0', location is LC1_A14, type is buried.
kk0 = DFFE( _EQ001, GLOBAL( clk), VCC, VCC, VCC);
_EQ001 = _LC7_A14 & !_LC8_A24
# a0 & _LC8_A24;
-- Node name is ':45' = 'kk1'
-- Equation name is 'kk1', location is LC6_A19, type is buried.
kk1 = DFFE( _EQ002, GLOBAL( clk), VCC, VCC, VCC);
_EQ002 = _LC8_A19 & !_LC8_A24
# a1 & _LC8_A24;
-- Node name is ':44' = 'kk2'
-- Equation name is 'kk2', location is LC2_A24, type is buried.
kk2 = DFFE( _EQ003, GLOBAL( clk), VCC, VCC, VCC);
_EQ003 = _LC7_A24 & !_LC8_A24
# a2 & _LC8_A24;
-- Node name is ':43' = 'kk3'
-- Equation name is 'kk3', location is LC6_A16, type is buried.
kk3 = DFFE( _EQ004, GLOBAL( clk), VCC, VCC, VCC);
_EQ004 = _LC7_A16 & !_LC8_A24
# a3 & _LC8_A24;
-- Node name is ':49' = 'qqq0'
-- Equation name is 'qqq0', location is LC1_A19, type is buried.
qqq0 = DFFE( _EQ005, GLOBAL( clk), VCC, VCC, VCC);
_EQ005 = !_LC2_A19
# _LC8_A24;
-- Node name is ':48' = 'qqq1'
-- Equation name is 'qqq1', location is LC8_A15, type is buried.
qqq1 = DFFE( _EQ006, GLOBAL( clk), VCC, VCC, VCC);
_EQ006 = qqq0 & !qqq1
# !qqq0 & qqq1 & !qqq2;
-- Node name is ':47' = 'qqq2'
-- Equation name is 'qqq2', location is LC6_A15, type is buried.
qqq2 = DFFE( _EQ007, GLOBAL( clk), VCC, VCC, VCC);
_EQ007 = qqq0 & qqq1 & !qqq2
# !qqq1 & qqq2;
-- Node name is 'speak'
-- Equation name is 'speak', type is output
speak = _LC3_A14;
-- Node name is ':26'
-- Equation name is '_LC7_A15', type is buried
_LC7_A15 = DFFE( _EQ008, GLOBAL( clk), VCC, VCC, VCC);
_EQ008 = !qqq0 & !qqq1 & !qqq2
# qqq1 & qqq2;
-- Node name is ':28'
-- Equation name is '_LC5_A13', type is buried
_LC5_A13 = DFFE( _EQ009, GLOBAL( clk), VCC, VCC, VCC);
_EQ009 = qqq0 & !qqq1 & !qqq2;
-- Node name is ':30'
-- Equation name is '_LC2_A15', type is buried
_LC2_A15 = DFFE( _EQ010, GLOBAL( clk), VCC, VCC, VCC);
_EQ010 = !qqq0 & qqq1 & !qqq2;
-- Node name is ':32'
-- Equation name is '_LC4_A15', type is buried
_LC4_A15 = DFFE( _EQ011, GLOBAL( clk), VCC, VCC, VCC);
_EQ011 = qqq0 & qqq1 & !qqq2;
-- Node name is ':34'
-- Equation name is '_LC3_A15', type is buried
_LC3_A15 = DFFE( _EQ012, GLOBAL( clk), VCC, VCC, VCC);
_EQ012 = _LC1_A15 & qqq2
# _LC1_A15 & !qqq1
# _LC1_A15 & !qqq0;
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