colordisplay.rpt

大学vhdl语言实验大全,基于max-plus2平台,内有8-3译码器,8位加法器,数字钟

   -      2     -    B    06       AND2    s           0    2    0    3  ~949~1
   -      4     -    B    08       AND2    s           0    3    0    1  ~949~2
   -      7     -    B    05        OR2    s           0    2    0    3  ~953~1
   -      7     -    B    08        OR2                0    4    0    1  :982
   -      6     -    B    07       AND2    s           0    4    0    1  ~1009~1
   -      8     -    B    07        OR2                0    4    0    1  :1009
   -      1     -    B    07        OR2                0    4    0    2  :1277
   -      2     -    B    08        OR2    s   !       0    3    0    3  ~1300~1
   -      5     -    B    07        OR2    s   !       0    3    0    3  ~1300~2
   -      4     -    B    12        OR2                0    4    0    3  :1322
   -      2     -    B    07       AND2                0    4    0    1  :1336
   -      2     -    B    12        OR2                0    2    0    2  :1373
   -      3     -    B    12        OR2                0    4    0    1  :1381
   -      6     -    B    12        OR2                0    4    0    1  :1397
   -      7     -    B    04        OR2                0    4    0    1  :1438
   -      6     -    B    04        OR2                0    4    0    1  :1445
   -      4     -    B    02        OR2                0    4    0    1  :1456
   -      7     -    B    02        OR2                0    4    0    1  :1462


Code:

s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register


Device-Specific Information:                  e:\tt\tt\eclock\colordisplay.rpt
colordisplay

** FASTTRACK INTERCONNECT UTILIZATION **

Row FastTrack Interconnect:

          Global         Left Half-      Right Half-
         FastTrack       FastTrack       FastTrack 
Row     Interconnect    Interconnect    Interconnect    Input Pins     Output Pins     Bidir Pins
A:       0/ 96(  0%)     0/ 48(  0%)     0/ 48(  0%)    0/16(  0%)      0/16(  0%)     0/16(  0%)
B:       5/ 96(  5%)    39/ 48( 81%)     0/ 48(  0%)    0/16(  0%)      6/16( 37%)     0/16(  0%)
C:       0/ 96(  0%)     0/ 48(  0%)     0/ 48(  0%)    0/16(  0%)      0/16(  0%)     0/16(  0%)


Column FastTrack Interconnect:

         FastTrack                                 
Column  Interconnect    Input Pins     Output Pins     Bidir Pins
01:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
02:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
03:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
04:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
05:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
06:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
07:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
08:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
09:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
10:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
11:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
12:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
13:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
14:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
15:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
16:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
17:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
18:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
19:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
20:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
21:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
22:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
23:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
24:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
EA:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)


Device-Specific Information:                  e:\tt\tt\eclock\colordisplay.rpt
colordisplay

** CLOCK SIGNALS **

Type     Fan-out       Name
INPUT       11         clk


Device-Specific Information:                  e:\tt\tt\eclock\colordisplay.rpt
colordisplay

** EQUATIONS **

clk      : INPUT;

-- Node name is 'd0' 
-- Equation name is 'd0', type is output 
d0       =  _LC3_B7;

-- Node name is 'd1' 
-- Equation name is 'd1', type is output 
d1       =  _LC1_B8;

-- Node name is 'd2' 
-- Equation name is 'd2', type is output 
d2       =  _LC4_B1;

-- Node name is 'd3' 
-- Equation name is 'd3', type is output 
d3       =  _LC1_B1;

-- Node name is 'd4' 
-- Equation name is 'd4', type is output 
d4       =  _LC8_B8;

-- Node name is 'd5' 
-- Equation name is 'd5', type is output 
d5       =  _LC6_B2;

-- Node name is ':21' = 'kkk0' 
-- Equation name is 'kkk0', location is LC6_B5, type is buried.
kkk0     = DFFE( _EQ001, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ001 = !_LC1_B10 &  _LC7_B2
         # !_LC1_B10 &  _LC4_B5
         #  _LC5_B10;

-- Node name is ':20' = 'kkk1' 
-- Equation name is 'kkk1', location is LC1_B12, type is buried.
kkk1     = DFFE( _EQ002, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ002 = !_LC5_B10 &  _LC6_B12 &  _LC8_B12
         # !_LC5_B10 &  _LC7_B5;

-- Node name is ':19' = 'kkk2' 
-- Equation name is 'kkk2', location is LC7_B7, type is buried.
kkk2     = DFFE( _EQ003, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ003 =  _LC2_B7 & !_LC5_B10 & !_LC7_B5
         # !_LC5_B7 & !_LC5_B10 & !_LC7_B5;

-- Node name is ':18' = 'kkk3' 
-- Equation name is 'kkk3', location is LC4_B7, type is buried.
kkk3     = DFFE( _EQ004, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ004 =  _LC1_B7 &  _LC5_B7 & !_LC5_B10 & !_LC7_B5;

-- Node name is ':17' = 'kkk4' 
-- Equation name is 'kkk4', location is LC8_B5, type is buried.
kkk4     = DFFE( _LC2_B10, GLOBAL( clk),  VCC,  VCC,  VCC);

-- Node name is ':2' 
-- Equation name is '_LC6_B2', type is buried 
_LC6_B2  = DFFE( _EQ005, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ005 = !_LC1_B10 & !_LC5_B10 &  _LC8_B2
         # !_LC1_B10 &  _LC4_B5 & !_LC5_B10;

-- Node name is ':4' 
-- Equation name is '_LC8_B8', type is buried 
_LC8_B8  = DFFE( _EQ006, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ006 =  _LC2_B8 & !_LC5_B10 &  _LC5_B12
         #  _LC3_B8 & !_LC5_B10;

-- Node name is ':6' 
-- Equation name is '_LC1_B1', type is buried 
_LC1_B1  = DFFE( _EQ007, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ007 =  _LC1_B2 & !_LC4_B10 &  _LC8_B1
         #  _LC3_B5;

-- Node name is ':8' 
-- Equation name is '_LC4_B1', type is buried 
_LC4_B1  = DFFE( _EQ008, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ008 =  _LC3_B5
         #  _LC1_B2 &  _LC2_B6 &  _LC3_B1;

-- Node name is ':10' 
-- Equation name is '_LC1_B8', type is buried 
_LC1_B8  = DFFE( _EQ009, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ009 =  _LC3_B8 & !_LC5_B10
         #  _LC4_B8 & !_LC5_B10 &  _LC6_B8;

-- Node name is ':12' 
-- Equation name is '_LC3_B7', type is buried 
_LC3_B7  = DFFE( _EQ010, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ010 = !_LC1_B10 & !_LC5_B10 &  _LC8_B7
         # !_LC1_B10 &  _LC4_B5 & !_LC5_B10;

-- Node name is ':388' 
-- Equation name is '_LC5_B5', type is buried 
!_LC5_B5 = _LC5_B5~NOT;
_LC5_B5~NOT = LCELL( _EQ011);
  _EQ011 = !kkk4
         #  kkk0
         #  _LC3_B10;

-- Node name is ':408' 
-- Equation name is '_LC2_B10', type is buried 
_LC2_B10 = LCELL( _EQ012);
  _EQ012 =  kkk1 &  kkk2 &  kkk3 &  _LC1_B5;

-- Node name is '~428~1' 
-- Equation name is '~428~1', location is LC2_B5, type is buried.
-- synthesized logic cell 
!_LC2_B5 = _LC2_B5~NOT;
_LC2_B5~NOT = LCELL( _EQ013);
  _EQ013 =  kkk4
         #  kkk0;

-- Node name is ':428' 
-- Equation name is '_LC4_B4', type is buried 
_LC4_B4  = LCELL( _EQ014);
  _EQ014 =  kkk1 &  kkk2 &  kkk3 &  _LC2_B5;

-- Node name is ':448' 
-- Equation name is '_LC6_B11', type is buried 
_LC6_B11 = LCELL( _EQ015);
  _EQ015 =  kkk3 & !_LC7_B10;

-- Node name is '~488~1' 
-- Equation name is '~488~1', location is LC1_B5, type is buried.
-- synthesized logic cell 
_LC1_B5  = LCELL( _EQ016);
  _EQ016 =  kkk0 & !kkk4;

-- Node name is ':508' 
-- Equation name is '_LC1_B4', type is buried 
_LC1_B4  = LCELL( _EQ017);
  _EQ017 =  kkk3 & !_LC8_B4;

-- Node name is ':528' 
-- Equation name is '_LC6_B10', type is buried 
_LC6_B10 = LCELL( _EQ018);
  _EQ018 = !kkk1 & !kkk2 &  kkk3 &  _LC1_B5;

-- Node name is ':548' 
-- Equation name is '_LC5_B4', type is buried 
!_LC5_B4 = _LC5_B4~NOT;
_LC5_B4~NOT = LCELL( _EQ019);
  _EQ019 = !kkk3
         #  kkk2
         #  kkk1
         # !_LC2_B5;

-- Node name is ':568' 
-- Equation name is '_LC4_B10', type is buried 
!_LC4_B10 = _LC4_B10~NOT;
_LC4_B10~NOT = LCELL( _EQ020);
  _EQ020 = !kkk1
         # !_LC1_B5
         #  kkk3
         # !kkk2;

-- Node name is ':588' 
-- Equation name is '_LC3_B2', type is buried 
_LC3_B2  = LCELL( _EQ021);
  _EQ021 =  kkk1 &  kkk2 & !kkk3 &  _LC2_B5;

-- Node name is ':593' 
-- Equation name is '_LC5_B2', type is buried 
_LC5_B2  = LCELL( _EQ022);
  _EQ022 = !_LC1_B7 & !_LC2_B10 &  _LC6_B2
         # !_LC1_B7 & !_LC2_B10 &  _LC5_B5;

-- Node name is '~608~1' 
-- Equation name is '~608~1', location is LC7_B10, type is buried.
-- synthesized logic cell 
!_LC7_B10 = _LC7_B10~NOT;
_LC7_B10~NOT = LCELL( _EQ023);
  _EQ023 = !kkk1 &  kkk2 &  _LC1_B5;

-- Node name is ':608' 
-- Equation name is '_LC2_B2', type is buried 
_LC2_B2  = LCELL( _EQ024);
  _EQ024 = !kkk3 & !_LC7_B10;

-- Node name is '~628~1' 
-- Equation name is '~628~1', location is LC3_B4, type is buried.
-- synthesized logic cell 
_LC3_B4  = LCELL( _EQ025);
  _EQ025 = !kkk2
         #  kkk1
         # !_LC2_B5;

-- Node name is '~648~1' 
-- Equation name is '~648~1', location is LC8_B10, type is buried.
-- synthesized logic cell 
_LC8_B10 = LCELL( _EQ026);
  _EQ026 =  kkk2
         # !kkk1
         # !_LC1_B5;

-- Node name is '~668~1' 
-- Equation name is '~668~1', location is LC8_B4, type is buried.
-- synthesized logic cell 
!_LC8_B4 = _LC8_B4~NOT;
_LC8_B4~NOT = LCELL( _EQ027);
  _EQ027 =  kkk1 & !kkk2 &  _LC2_B5;

-- Node name is ':668' 
-- Equation name is '_LC4_B5', type is buried 
_LC4_B5  = LCELL( _EQ028);
  _EQ028 = !kkk3 & !_LC8_B4;

-- Node name is '~673~1' 
-- Equation name is '~673~1', location is LC8_B12, type is buried.
-- synthesized logic cell 
_LC8_B12 = LCELL( _EQ029);
  _EQ029 =  kkk3
         #  _LC3_B4 &  _LC8_B10;

-- Node name is ':673' 
-- Equation name is '_LC8_B2', type is buried 
_LC8_B2  = LCELL( _EQ030);
  _EQ030 = !_LC2_B2 &  _LC5_B2 &  _LC8_B12
         # !_LC2_B2 &  _LC3_B2 &  _LC8_B12;

-- Node name is ':688' 
-- Equation name is '_LC1_B10', type is buried 
_LC1_B10 = LCELL( _EQ031);
  _EQ031 =  _LC1_B5 & !_LC3_B10;

-- Node name is '~708~1' 
-- Equation name is '~708~1', location is LC3_B10, type is buried.
-- synthesized logic cell 
_LC3_B10 = LCELL( _EQ032);
  _EQ032 =  kkk3
         #  kkk2
         #  kkk1;

-- Node name is ':708'